MC9328MXL datasheet(72/84 Pages) FREESCALE

72 / 84 page

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor

Specifications

STCK high to STXD high impedance

18.47

28.5

16.2

25.0

SRXD setup time before SRCK low

1.14

–

1.0

–

SRXD hole time after SRCK low

–

Synchronous Internal Clock Operation (Port C Primary Function2)

SRXD setup before STCK falling

15.4

–

13.5

–

SRXD hold after STCK falling

–

Synchronous External Clock Operation (Port C Primary Function2)

SRXD setup before STCK falling

1.14

–

1.0

–

SRXD hold after STCK falling

–

All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a

non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been

inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync

STFS/SRFS shown in the tables and in the figures.

There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad

261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they

can be viewed both at Port C primary function and Port B alternate function. When SSI signals are

configured as input, the SSI module selects the input based on status of the FMCR register bits in the

Clock controller module (CRM). By default, the input are selected from Port C primary function.

bl = bit length; wl = word length.

Table 30. SSI (Port B Alternate Function) Timing Parameter Table

Ref

No.

Parameter

1.8V ± 0.10V

3.0V ± 0.30V

Unit

Minimum

Maximum

Minimum

Maximum

Internal Clock Operation1 (Port B Alternate Function2)

STCK/SRCK clock period1

–

83.3

–

STCK high to STFS (bl) high3

1.7

4.8

1.5

4.2

SRCK high to SRFS (bl) high3

-0.1

1.0

-0.1

1.0

STCK high to STFS (bl) low3

3.08

5.24

2.7

4.6

SRCK high to SRFS (bl) low3

1.25

2.28

1.1

2.0

STCK high to STFS (wl) high3

1.71

4.79

1.5

4.2

SRCK high to SRFS (wl) high3

-0.1

1.0

-0.1

1.0

STCK high to STFS (wl) low3

3.08

5.24

2.7

4.6

Table 29. SSI (Port C Primary Function) Timing Parameter Table (Continued)

Ref No.

Parameter

1.8V ± 0.10V

3.0V ± 0.30V

Unit

Minimum

Maximum

Minimum

Maximum

MC9328MXL Folha de dados(PDF) 72 Page - Freescale Semiconductor, Inc

MC9328MXL Folha de dados(HTML) 72 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Folha de dados Download

Ligação URL