MC9328MXL datasheet(68/84 Pages) FREESCALE

68 / 84 page

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor

Specifications

3.17 I2C Module

The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data

Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.

Figure 54. Definition of Bus Timing for I2C

3.18 Synchronous Serial Interface

The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode,

the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous

mode, the transmitter and receiver each have their own clock and frame synchronization signals.

Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In

gated clock mode, the clock functions only during transmission. The internal and external clock timing

diagrams are shown in Figure 56 through Figure 58 on page 70.

Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of

I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is

typically used in star or ring-time division multiplex networks with other processors or codecs, allowing

interface to time division multiplexed networks without additional logic. Use of the gated clock is not

allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to

communicate with a wide variety of devices.

Table 28. I2C Bus Timing Parameter Table

Ref No.

Parameter

1.8V ± 0.10V

3.0V ± 0.30V

Unit

Minimum

Maximum

Minimum

Maximum

Hold time (repeated) START condition

182

–

160

–

Data hold time

01710150

Data setup time

11.4

–

HIGH period of the SCL clock

–

120

–

LOW period of the SCL clock

480

–

320

–

Setup time for STOP condition

182.4

–

160

–

SDA

SCL

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