MC9328MXL datasheet(74/84 Pages) FREESCALE

74 / 84 page

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor

Specifications

Synchronous Internal Clock Operation (Port B Alternate Function2)

SRXD setup before STCK falling

18.81

–

16.5

–

SRXD hold after STCK falling

–

Synchronous External Clock Operation (Port B Alternate Function2)

SRXD setup before STCK falling

1.14

–

1.0

–

SRXD hold after STCK falling

–

All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a

non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been

inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync

STFS/SRFS shown in the tables and in the figures.

There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad

261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they

can be viewed both at Port C primary function and Port B alternate function. When SSI signals are

configured as inputs, the SSI module selects the input based on FMCR register bits in the Clock controller

module (CRM). By default, the input are selected from Port C primary function.

bl = bit length; wl = word length.

Table 30. SSI (Port B Alternate Function) Timing Parameter Table (Continued)

Ref

No.

Parameter

1.8V ± 0.10V

3.0V ± 0.30V

Unit

Minimum

Maximum

Minimum

Maximum

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