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MC9328MXL Folha de dados(PDF) 47 Page - Freescale Semiconductor, Inc |
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MC9328MXL Folha de dados(HTML) 47 Page - Freescale Semiconductor, Inc |
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47 / 84 page ![]() Specifications MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 47 Figure 35. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge 3.11 LCD Controller This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller with various display configurations, refer to the LCD controller chapter of the MC9328MXL Reference Manual. Figure 36. SCLK to LD Timing Diagram Table 15. Timing Parameter Table for Figure 31 through Figure 35 Ref No. Parameter 1.8V ± 0.10V 3.0V ± 0.30V Unit Minimum Maximum Minimum Maximum 1 SPI_RDY to SS output low 2T 1 1. T = CSPI system clock period (PERCLK2). – 2T1 –ns 2SS output low to first SCLK edge 3 • Tsclk 2 2. Tsclk = Period of SCLK. – 3 • Tsclk2 –ns 3 Last SCLK edge to SS output high 2 • Tsclk – 2 • Tsclk – ns 4SS output high to SPI_RDY low 0– 0– ns 5SS output pulse width Tsclk + WAIT 3 3. WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register. – Tsclk + WAIT3 –ns 6SS input low to first SCLK edge T–T– ns 7SS input pulse width T – T – ns 6 7 SS (input) SCLK, MOSI, MISO 1 LSCLK LD[15:0] |
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