GD32H757ZMT7 datasheet(89/151 Pages) GIGADEVICE

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GD32H757xx Datasheet

fAPB1

APB1 clock frequency

—

150(2)

fAPB2

APB2 clock frequency

—

300(2)

fAPB3

APB3 clock frequency

—

150(2)

fAPB4

APB4 clock frequency

—

150(2)

(1)

Value guaranteed by design, not 100% tested in production.

(2)

APBx clocks are divided from AHB clock.

Table 4-6. TCM interface frequency(1)

Symbol

Parameter

Conditions

Min

Max

Unit

fTWW

TCM without wait

—

350

MHz

(1)

Value guaranteed by design, not 100% tested in production.

Table 4-7. Operating conditions at Power up / Power down(1)

Symbol

Parameter

Conditions

Min

Max

Unit

tVDD

VDD rise time rate

—

∞

μs/V

VDD fall time rate

100

∞

tVDDA

VDDA rise time rate

—

∞

VDDA fall time rate

100

∞

tVDD(USB)

VDD(USB) rise time rate

—

∞

VDD(USB) fall time rate

100

∞

(1)

Value guaranteed by design, not 100% tested in production.

4.3.

Power consumption

The power measurements specified in the tables represent that code with data executing from

on-chip Flash with the following specifications.

Table 4-8.

Power consumption characteristics(1)(2)(3)(4)

Symbol

Parameter

Conditions

Typ LDO

regulator

Max

Unit

IDD+IDDA

Supply current

(Run mode)

VDD = VDDA = 3.3 V, System clock =

600 MHz, All peripherals enabled,

code run in ITCM

161

—

VDD = VDDA = 3.3 V, System clock =

600 MHz, All peripherals enabled,

code run in Flash and cache on

151

—

VDD = VDDA = 3.3 V, System clock =

600 MHz, All peripherals enabled,

code run in Flash and cache off

151

—

VDD = VDDA = 3.3 V, System clock =

600 MHz, All peripherals disabled,

code run in ITCM

47.5

—

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