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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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GD32H757ZMT7 Folha de dados(PDF) 25 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD32H757ZMT7 Folha de dados(HTML) 25 Page - GigaDevice Semiconductor (Beijing) Inc. |
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25 / 151 page  GD32H757xx Datasheet 24 2.5. Clock tree Figure 2-5. GD32H757xx clock tree 32.768 KHz LXTAL OSC 11 10 01 32 KHz IRC32K CK_RTC CK_FWDGT (to RTC) (to FWDGT) /2 to /63 RTCSRC[1:0] CK_OUT1 CK_PLL0P CK_HXTAL CK_SYS CK_PLL1R 011 000 001 010 CKOUT1SEL[2:0] CKOUT1DIV ÷1,2,3...15 CK_HXTAL RTCDIV[5:0] CK_DAC (to DAC) 100 101 CK_IRC32K CK_LPIRC4M CK_OUT0 CK_PLL0P CK_HXTAL CK_IRC64MDI V CK_LXTAL 011 000 001 010 CKOUT0SEL[2:0] CKOUT0DIV ÷1,2,3...15 CK_IRC48M 4-50 MHz HXTAL 64 MHz IRC64M Clock Monit or CK_IRC64MDI V CK_HXTAL CK_PLL0P SCS[1:0] 00 01 10 IRC64MDI V ÷1,2,4,8 11 CK_LPIRC4M 4 MHz LPIRC4M 00 01 PLLSEL[1:0] 10 CK_SYS 600 MHz max xN VCO /P /Q /R PLL0 xN VCO /P /Q /R PLL1 xN VCO /P /Q /R PLL2 0 1 PLL48MSEL PLL2RDIV ÷2,4,8,16 0 1 0 1 /2 or /20 ENETx_PHY_SEL ENETx_TX_CLK ENETx_RX_CLK CK_ENETxTX to ENETx TX Peripheral enable CK_ENETxRX to ENETx RX Peripheral enable CK_USBHS to USBHSx Peripheral enable USB HS PHY clock 24Mhz t o 60Mhz 0 1 EMBPHY_HS 0 1 USBHSx 60M (6) CK_PLLUSBHSx CK_IRC48M USBHSx48MSEL[1:0] Prescaler ÷2,4...16 USBHSxDV x16,17... 127 Prescaler ÷1,2...15 PLLUSBHSxMF PLLUSBHSxPREDV 0 1 PLLUSBHSxPRESEL CK_IRC48M CK_HXTAL AHB/AXI Prescaler ÷1,2...512 ÷8 CK_CST (to Cortex-M7 SysTick) FCLK ACLK to AXI peripherals HCLK to AHB bus, Cortex-M7, SRAM, DMA, peripherals AXI enable AHB enable APB3 Prescaler ÷1,2,4,8,16 to APB3 peripherals PCLK3 to OSPI CK_OSPI Peripheral enable to TRNG 48 MHz IRC48M 1 0 CTC CK48MSEL CK_CTC Peripheral enable CK_48M APB2 Prescaler ÷1,2,4,8,16 CK_APB2 300 MHz max Peripheral enable PCLK2 to APB2 peripherals 150 MHz max APB4 Prescaler ÷1,2,4,8,16 to APB4 peripherals PCLK4 to LPDTS CK_LPDTS to TLI CK_TLI Peripheral enable USBHSxSEL CK_HXTAL CK_IRC64MDI V CANxSEL[1:0] 00 01 10 11 CK_APB2 / 2 to CANx Peripheral enable CK_CAN CK_APBx(x=1,2) CK_AHB CK_IRC64MDI V USARTxSEL[1:0] 00 01 10 11 CK_LXTAL to USARTx Peripheral enable CK_USART CK_PLL0Q CK_PLL1P I2S_CKIN SAI2B0SEL[2:0] or SAI2B1SEL[2:0] 000 001 CK_PLL2P Peripheral enable CK_SAI2B0 or CK_SAI2B1 010 011 100 101 to SAI2_B0 or SAI2_B1 CK_PER CK_PLL0Q CK_PLL1P I2S_CKIN SAI0SEL[2:0] or SAI1SEL[2:0] 000 001 CK_PLL2P Peripheral enable CK_SAI0 or CK_SAI1 010 011 100 to SAI0 or SAI1 CK_PER CK_APB4 150 MHz max 300 MHz max 300 MHz max Peripheral enable Peripheral enable CK_IRC64MDI V CK_LPIRC4M PERSEL[1:0] 00 01 10 CK_PER (2) CK_HXTAL (free running clock) CK_USBHS_ULPI to USBHS ULPI Peripheral enable CK_APB1 CK_PLL2R CK_LPIRC4M I2CxSEL[1:0] 00 01 10 11 CK_IRC64MDI V to I2Cx Peripheral enable CK_I2C CK_RSPDIF_SYMB (4) CK_APB2 Peripheral enable CK_HPDFAUDIO to HPDFAUDIO CK_PLL0Q CK_PLL1R CK_IRC64MDI V RSPDIFSEL[1:0] 00 01 10 11 CK_PLL2R to RSPDIF Peripheral enable CK_RSPDIF CK_PLL1P to EFUSE Peripheral enable CK_EFUSE CK_IRC64MDI V I2S_CKIN 100 CK_PER 101 USBHS0 60M 110 111 USBHS1 60M /PLL0PSC /PLL1PSC /PLL2PSC APB1 Prescaler ÷1,2,4,8,16 CK_APB1 150 MHz max PCLK1 to APB1 peripherals 0 1 REFSEL (1) CK_LXTAL CK_APB3 00 01 10 11 CK_PLL0R Prescaler ÷1,2...8 CK_PLL1Q CK_PLL1Q CK_PLL0Q TIMER0,7,14,15,1 6,40,41,42,43,44 (CK_APB2×1 ×2 or ×4) TIMERx enable CK_TIMERx to TIMER0,7,14,15,1 6,40,41,42,43,44 300 MHz max CK_PLL0R CK_IRC48M USBHSxPSC CK_PLL0R SCS[1:0] 11 CK_LPIRC4M CK_TPIU (3) 00 01 10 CK_IRC64MDI V CK_HXTAL Peripheral enable TIMER1,2,3,4,5,6,2 2,23,30,31,50,51 (CK_APB1×1 ×2 or ×4) TIMERx enable CK_TIMERx to TIMER1,2,3,4,5,6, 22,23,30,31,50,51 300 MHz max CK_ADCx ADCxSEL[1:0] 00 01 10 1010 0000 1000 1001 1011 HCLK/2 HCLK/4 HCLK/6 HCLK/8 CK_PLL1P CK_PLL2R CK_PER ADCSCK (5)[3:0] CK_AHB/AXI 300 MHz max 1100 1101 HCLK/10 HCLK/12 HCLK/14 HCLK/16 1110 1111 0 1 HPDFSEL CK_HPDF CK_AHB CK_APB2 to HPDF Peripheral enable CK_AHB CK_PLL0Q CK_PER EXMCSEL[1:0] 00 01 10 11 CK_PLL1R to EXMC Peripheral enable CK_EXMC 110 CK_PLL2R to SDIO x CK_SDIO Peripheral enable 0 1 SDIOxSEL CK_PLL1R CK_PLL0Q CK_PLL1R CK_SAI0 CK_PLL0Q CK_PLL1P I2S_CKIN SPIxSEL[2:0](x=0,1,2) 000 001 CK_PLL2P Peripheral enable CK_SPIx 010 011 100 to SPIx CK_PER CK_APB2 CK_PLL1Q CK_IRC64MDI V SPIxSEL[2:0](x=3,4) 000 001 CK_PLL2Q Peripheral enable CK_SPIx 010 011 100 101 to SPIx CK_HXTAL CK_LPIRC4M CK_APB2 CK_PLL1Q CK_IRC64MDI V SPI5SEL[2:0] 000 001 CK_PLL2Q Peripheral enable CK_SPI5 010 011 100 101 to SPI5 CK_HXTAL CK_LPIRC4M 110 I2S_CKIN to ADCx Peripheral enable CK_PLL2P CK_PLL2R CK_PLL0P 480 MHz max CK_PLL2Q Legend: HXTAL: High speed crystal oscillator LXTAL: Low speed crystal oscillator |
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