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GD32H757ZMT7 Folha de dados(PDF) 87 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD32H757ZMT7 Folha de dados(HTML) 87 Page - GigaDevice Semiconductor (Beijing) Inc. |
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87 / 151 page ![]() GD32H757xx Datasheet 86 Symbol Parameter Conditions Min(1) Typ Max(1) Unit VDDA Analog supply voltage Same as VDD 1.71 3.3 3.6 V VBAT Battery supply voltage — 1.71 — 3.6 V VCORE(2) VCORE supply voltage Bypass mode 0.873 0.9 0.955 V (1) Value guaranteed by characterization, not 100% tested in production. (2) The power-up and power-down sequence for the power bypass mode should meet the requirements as illustrated in Figure 4-1. Bypass Mode Power-up and Power-down Timing Diagram (1)(2)(3). Figure 4-1. Bypass Mode Power-up and Power-down Timing Diagram (1)(2)(3) POR threshold PDR threshold VC OR E > 0.85V VC OR E > 0.85V Mi n VC OR E at s tart up 0. 85V Mi n VC OR E at power down 0. 85V VDD/VDDA VCORE (1) Before the MCU's VDD/VDDA voltage rises to the POR (Power-On Reset) threshold, ensure that the VCORE voltage is greater than 0.85 V. (2) Before the MCU's VDD/VDDA voltage drops to the PDR (Power-Down Reset) threshold, ensure that the VCORE voltage is greater than 0.85 V (3) Under any operating condition, ensure that the VDD/VDDA voltage is greater than the VCORE voltage. |
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