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GD32H757ZMT7 Folha de dados(PDF) 68 Page - GigaDevice Semiconductor (Beijing) Inc.

Nome de Peças GD32H757ZMT7
Descrição Electrónicos  Arm® Cortex®-M7 32-bit MCU
PDF  151 Pages
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Fabricante Electrônico  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Página de início  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

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67
in LFSR mode.
32-bit random numbers are generated each time in LFSR mode.
TRNG NIST mode follows the NIST SP800-90B.
Support health tests recommended by the NIST SP800-90B.
32-bit*4 or 32-bit*8 random numbers are generated each time in NIST mode.
TRNG has the functions of startup and in-service self-check, associated with specific
error flags.
128-bit random value seed is generated from analog noise.
The true random number generator (TRNG) module can generate a 32-bit random value by
using continuous analog noise and it has been pre-certified NIST SP800-90B.
3.11.
Cryptographic Acceleration Unit (CAU)
 Supports DES, TDES or AES (128, 192, or 256) algorithms.
DES/TDES supports Electronic codebook (ECB) or Cipher block chaining (CBC) mode.
AES supports 128bits-key, 192bits-key or 256 bits-key.
Multiple modes are supported respectively in DES, TDES and AES, including Electronic
codebook (ECB), Cipher block chaining (CBC), Counter mode (CTR), Galois / counter
mode (GCM), Galois message authentication code mode (GMAC), Counter with CBC-
MAC (CCM), Cipher Feedback mode (CFB) and Output Feedback mode (OFB).
DMA transfer for incoming and outgoing data is supported.
The cryptographic acceleration unit (CAU) is used to encipher and decipher data with DES,
Triple-DES or AES (128, 192, or 256) algorithms. DES / TDES / AES algorithms with different
key sizes are supported to perform data encryption and decryption in the CAU in multiple
modes. The CAU is a 32-bit peripheral, DMA transfer is supported and data can be accessed
in the input and output FIFO.
3.12.
Hash Acceleration Unit (HAU)
Federal Information Processing Standards Publication 180-4(FIPS PUB 180-4).
Secure Hash Standard specifications (SHA-1, SHA-224, SHA-256).
Internet Engineering Task Force Request for Comments number 1321 (IETF RFC
1321) specifications (MD5).
High performance of computation of hash algorithms.
Automatic data padding to fill the 512-bit message block for digest computation.
DMA transfer is supported.
Hash / HMAC process suspended mode.
The hash acceleration unit (HAU) is used for information security. The secure hash algorithm
(SHA-1, SHA-224, SHA-256), the message-digest algorithm (MD5) and the keyed-hash
message authentication code (HMAC) algorithm are supported for various applications. The
digest will be computed and the length is 160 / 224 / 256 / 128 bits for a message up to (264



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