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GD32H757ZMT7 Folha de dados(PDF) 71 Page - GigaDevice Semiconductor (Beijing) Inc.

Nome de Peças GD32H757ZMT7
Descrição Electrónicos  Arm® Cortex®-M7 32-bit MCU
PDF  151 Pages
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Fabricante Electrônico  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Página de início  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD32H757ZMT7 Folha de dados(HTML) 71 Page - GigaDevice Semiconductor (Beijing) Inc.

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GD32H757xx Datasheet
70
3.3V, ADC2 supply requirements: 1.71V to 3.6V, typical power supply voltage is 3.3V.
ADC input voltage range: VREFN ≤VIN ≤VREFP.
Temperature sensor.
Start-of-conversion can be initiated by software or TRIGSEL.
A 12 / 14-bit successive approximation analog-to-digital converter module (ADC) is integrated
on the MCU chip. ADC0 has 20 external channels, 1 internal channel (DAC_OUT0 channel),
ADC1 has 18 external channels, 3 internal channels (the battery voltage, VREFINT inputs
channel and DAC_OUT1 channel), ADC2 has 17 external channels, 4 internal channels (the
battery voltage, VREFINT inputs channel, tempeture sensor and high-precision tempeture
sensor). After sampling and conversion, the conversion results can be stored in the
corresponding data registers according to the least significant bit (LSB) alignment or the most
significant (MSB) bit alignment (ADC0 / 1 are 32-bit data register, ADC2 is 16-bit data register).
An on-chip hardware oversample scheme improves performances and reduces the
computational burden of MCU.
3.18.
Digital to analog converter (DAC)
8-bit or 12-bit resolution. Left or right data alignment.
Conversion update synchronously.
Conversion trigged by external triggers.
Input voltage reference, VREFP.
Output buffer calibration.
Using sample and keep mode to reduce the power consumption.
Noise wave generation (LFSR noise mode and Triangle noise mode).
Two DAC channels in concurrent mode.
The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins.
The digital data can be set to 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA
can be used to update the digital data on external triggers. The output voltage can be
optionally buffered for higher drive capability, and DAC output buffer can be calibrated to
improve output accuracy. The sample and keep mode can reduce the power consumption of
DAC.
3.19.
Real time clock (RTC) and backup registers
Support calendar function, which can support year, month, date, day, hours, minutes,
seconds and subseconds (date is the day of week and day is the day of month).
Daylight saving compensation supported, which is realized through software.
External high-accurate low frequency (50Hz or 60Hz) clock used to achieve higher
calendar accuracy performed by reference clock detection option function.
Atomic clock adjust (max adjust accuracy is 0.95PPM) for calendar calibration performed
by digital calibration function.



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