GD32H757ZMT7 datasheet(75/151 Pages) GIGADEVICE

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GD32H757xx Datasheet

3.24.

Inter-IC sound (I2S)



Master or slave operation for transmission/reception.



Four I2S standards supported: Phillips, MSB justified, LSB justified and PCM standard.



Data length can be 16 bits, 24 bits or 32 bits.



Channel length can be 16 bits or 32 bits.



Transmission and reception use a 32 bits wide buffer.



Audio sample frequency can be 8 kHz to 192 kHz using I2S clock divider.



Programmable idle state clock polarity.



Separate transmit and receive 32-bit FIFO.

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio

applications by 4-wire serial lines. GD32H757xx contain an I2S-bus interface that can be

operated with 16/32 bit resolution in master or slave mode,

pin multiplexed with SPI1 and

SPI2. The audio sampling frequencies from 8 KHz to 192 KHz is supported.

3.25.

OSPI I/O manager(OSPIM)



Supports two OSPI (single-line, two-lines, four-lines, eight-lines) interfaces.



Support two ports for pin assignment.



Fully programmable IO matrix, can assign pins according to function.

OSPIM supports OSPI pin assignment with full matrix.

3.26.

Octal-SPI interface(OSPI)



Three functional modes:

indirect mode, status polling mode, memory-mapped mode.



Support read in

memory-mapped mode.



Support single, dual, quad and octal communication.



Fully programmable command format for both indirect and memory-mapped mode.



Support SDR (signal data rate) and DTR (double transfer rate, only for GD25LX512ME).



Integrated FIFO for transmission/reception.



8, 16 and 32-bits data access.

The OSPI is a specialized interface that communicate with external memories. The interface

support single, dual, quad and octal SPI flash (PSRAMS, NAND, NOR Flash, etc).

3.27.

Clock phase delay module (CPDM)



Supports the input clock frequency ranges: 25 MHz ~ 208MHz.



Supports up to 12 oversampling phases.

The Clock Phase Delay Module (CPDM) is used to delay the phase of the input clock and

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