GD32H757ZMT7 datasheet(78/151 Pages) GIGADEVICE

78 / 151 page

GD32H757xx Datasheet

The IPA provides a configurable and flexible image format conversion from one or two source

image to the destination image. Sixteen pixel formats for foreground from 4-bit up to 32-bit

per pixel, eleven pixel formats for background from 4-bit up to 32-bit per pixel, and five pixel

formats from 16-bit up to 32-bit per pixel for the destination image are supported. Two 256*32

bits LUTs (Look-Up Table) separately for the two source images are implemented for the

indirect pixel formats.

3.33.

Secure digital input and output card interface (SDIO)



e•MMC: Support for embedded Multimedia Card System Specification Version 4.51 (and

previous versions) Card and five different data bus modes: 1-bit (default), 4-bit (SDR/DDR)

and 8-bit(SDR/DDR).



SD Card: Full support for SD Memory Card Specifications Version 3.0.



SD I/O: Full support for SD I/O Card Specification Version 3.0 card and three different

data bus modes: 1-bit (default) and 4-bit (SDR/DDR).



104MHz data transfer frequency and 8-bit data transfer mode.



Support DDR and max clock frequency is 50Mhz.

The secure digital input/output interface (SDIO) defines the SD, SD I/O and embedded

MultiMediaCard (e•MMC) host interface, which provides command/data transfer between the

AHB system bus and SD memory cards, SD I/O cards and e•MMC.

3.34.

Management data input/output (MDIO)



Support slave mode with a frequency up to 4MHz.



Support CFP/CFP2 MSA Management Interface Specification.

The MDIO interface can receive complete MDIO frames. As long as the data is written to the

frame, the MDIO interface can transmit complete MDIO frames. Interrupts are generated at

the end of every complete frame, which can be used or provided at correct time. Interrupts

can also be generated after every valid PHYADR and DEVADD, which allows more complex

controls within frames.

3.35.

External memory controller (EXMC)



Supported external memory: SRAM, PSRAM, ROM, NOR-Flash, 8/16-bit NAND Flash

and Synchronous DRAM (SDRAM).



Embedded ECC hardware for NAND Flash access.



Two SDRAM banks with independent configuration, up to 13-bits Row Address, 11-bits

Column Address, 2-bits internal banks address.



SDRAM Memory size: 4x16Mx32bit (256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64

MB).

GD32H757ZMT7 Folha de dados(PDF) 78 Page - GigaDevice Semiconductor (Beijing) Inc.

GD32H757ZMT7 Folha de dados(HTML) 78 Page - GigaDevice Semiconductor (Beijing) Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL