GD32H757ZMT7 datasheet(74/151 Pages) GIGADEVICE

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GD32H757xx Datasheet

used for RS-232 standard communication. The USART/UART includes a programmable baud

rate generator which is capable of dividing the system clock to produce a dedicated clock for

the USART/UART transmitter and receiver.

3.22.

Inter-integrated circuit (I2C)



Up to three I2C bus interfaces can support both master and slave mode with a frequency

up to 1 MHz (Fast mode plus).



Provide arbitration function, optional PEC (packet error checking) generation and

checking.



Supports 7-bit and 10-bit addressing mode and general call addressing mode.



SMBus 3.0 and PMBus 1.3 compatible.



Wakeup from sleep mode and Deep-sleep mode on I2C address match.

The I2C (inter-integrated circuit) module provides an I2C interface which is an industry

standard two-line serial interface for MCU to communicate with external I2C interface. I2C

bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C

interface implements standard I2C protocol with standard mode (up to 100KHz), fast mode

(up to 400KHz) and fast mode plus (up to 1MHz) as well as CRC calculation and checking,

SMBus (system management bus), and PMBus (power management bus).

3.23.

Serial peripheral interface (SPI)



Master or slave operation with full-duplex, half-duplex or simplex mode.



Separate transmit and receive 32-bit FIFO.



Data frame size can be 4 to 32 bits.



Hardware CRC calculation, transmission and checking.



SPI TI mode supported.



Multi-master or multi-slave mode function.



Protect configurations and settings.



Adjustable main device receiver sampling time.



Configurable FIFO thresholds (data packing).



Quad-SPI configuration available in master mode (in SPI3 / 4).

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO

& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by

the DMA controller. The SPI interface may be used for a variety of purposes, including simplex

synchronous transfers on two lines with a possible bidirectional data line or reliable

communication using CRC checking. Quad-SPI master mode is also supported in SPI3 and

SPI4.

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