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DS3134

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4.3.2 STATUS & INTERRUPT REGISTER DESCRIPTION

0020h

5432

n/a

PPERR

PSERR

SBERT

STCOFA

SRCOFA

LBINT

LBE

n/a

Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.

Bit 0 / Status Bit for Receive Change Of Frame Alignment (SRCOFA). This status bit will be set to a

one if one or more of the receive ports has experienced a Change Of Frame Alignment (COFA) event.

The host must read the RCOFA bit in the Receive Port Control Registers (RP[n]CR) of each active port to

determine which port or ports has seen the COFA. The SRCOFA bit will be cleared when read and will

not be set again, until one or more receive ports has experienced another COFA. If enabled via the

SRCOFA bit in the Interrupt Mask for SM (ISM), the setting of this bit will cause a hardware interrupt at

the PCI Bus via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration

Mode.

Bit 1 / Status Bit for Transmit Change Of Frame Alignment (STCOFA). This status bit will be set to

a one if one or more of the transmit ports has experienced a Change Of Frame Alignment (COFA) event.

The host must read the TCOFA bit in the Transmit Port Control Registers (TP[n]CR) of each active port

to determine which port or ports has seen the COFA. The STCOFA bit will be cleared when read and

will not be set again, until one or more transmit ports has experienced another COFA. If enabled via the

STCOFA bit in the Interrupt Mask for SM (ISM), the setting of this bit will cause a hardware interrupt at

the PCI Bus via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration

Mode.

Bit 2 / Status Bit for Change of State in BERT (SBERT). This status bit will be set to a one if there is

a major change of state in the BERT receiver. A major change of state is defined as either a change in the

receive synchronization (i.e. the BERT has gone into or out of receive synchronization), a bit error has

been detected, or an overflow has occurred in either the Bit Counter or the Error Counter. The Host must

read the status bits of the BERT in the BERT Status Register (BERTEC0) to determine the change of

state. The SBERT bit will be cleared when read and will not be set again until the BERT has experienced

another change of state. If enabled via the SBERT bit in the Interrupt Mask for SM (ISM), the setting of

this bit will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT* if

the Local Bus is in the Configuration Mode.

Bit 3 / Status Bit for PCI System Error (PSERR). This status bit is a software version of the PCI Bus

hardware pin PSERR. It will be set to a one if the PCI Bus detects an address parity error or other PCI

Bus error. The PSERR bit will be cleared when read and will not be set again until another PCI Bus error

has occurred. If enabled via the PSERR bit in the Interrupt Mask for SM (ISM), the setting of this bit will

cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT* if the Local

Bus is in the Configuration Mode. This status bit is also reported in the Control/Status register in the PCI

Configuration registers, see Section 9 for more details.

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