DS3134 datasheet(12/203 Pages) DALLAS

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DS3134

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When the DMA begins burst writing data into the FIFO, it will try to completely fill the FIFO with HDLC

packet data even if it that means writing multiple packets. Once the FIFO detects that the DMA has filled

it to beyond the Low Water Mark (or an EOF is reached), the FIFO will begin transferring 32-bit dwords

to the HDLC Engine.

One of the unique attributes of the DS3134 is the structure of the DMA. The DMA has been optimized to

maintain maximum flexibility yet reduce the number of bus cycles required to transfer packet data. The

DMA uses a flexible scatter/gather technique, which allows that packet data to be place anywhere within

the 32-bit address space. The user has the option on the receive side of two different buffer sizes which

are called “large” and “small” but that can be set to any size up to 8191 bytes. The user has the option to

store the incoming data either, only in the large buffers, only in the small buffers, or fill a small buffer

first and then fill large buffers as needed. The varying buffer storage options allow the user to make the

best use of the available memory and to be able to balance the tradeoff between latency and bus

utilization.

The DMA uses a set of descriptors to know where to store the incoming HDLC packet data and where to

obtain HDLC packet data that is ready to be transmitted. The descriptors are fixed size messages that are

handed back and forth from the DMA to the Host. Since this descriptor transfer utilizes bus cycles, the

DMA has been structured to minimize the number of transfers required. For example on the receive side,

the DMA obtains descriptors from the Host to know where in the 32-bit address space to place the

incoming packet data. These descriptors are known as Free Queue Descriptors. When the DMA reads

these descriptors off of the PCI Bus, they contain all the information that the DMA needs to know where

to store the incoming data. Unlike other existing scatter/gather DMA architectures, the DS3134 DMA

does not need to use any more bus cycles to determine where to place the data. Other DMA architectures

tend to use pointers, which require them to go back onto the bus to obtain more information and hence

use more bus cycles.

Another technique that the DMA uses to maximize bus utilization is the ability to burst read and writes

the descriptors. The device can be enabled to read and write the descriptors in bursts of 8 or 16 instead of

one at a time. Since there is fixed overhead associated with each bus transaction, the ability to burst read

and write descriptors allows the device to share the bus overhead among 8 or 16 descriptor transactions

which reduces the total number of bus cycles needed.

The DMA can also burst up to 256 dwords (1024 bytes) onto the PCI Bus. This helps to minimize bus

cycles by allowing the device to burst large amounts of data in a smaller number of bus transactions

which reduces bus cycles by reducing the amount of fixed overhead that is placed on the bus.

The Local Bus Block has two modes of operation. It can be used as either a Bridge from the PCI Bus in

which case it is a bus master or it can be used as a Configuration Bus in which case it is a bus slave. The

Bridge Mode allows the Host on the PCI Bus to access the local bus. The DS3134 will map data from the

PCI Bus to the local bus. In the Configuration Mode, the local bus is used only to control and monitor the

DS3134 while the HDLC packet data will still be transferred to the Host via the PCI Bus.

Restrictions

In creating the overall system architecture, the user must balance the port, throughput, and HDLC channel

restrictions of the DS3134. Table 1D lists all of the upper bound maximum restrictions on the DS3134.

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