DS3134 datasheet(42/203 Pages) DALLAS

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DS3134

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SM Register

The Status Master (SM) register reports events that occur at the Port Interface, at the BERT receiver, at

the PCI Bus and at the Local Bus. See Figure 4.3.1A for details.

The Port Interface reports Change Of Frame Alignment (COFA) events. If the software detects that one

of these bits as being set, the software must then begin polling the RP[n]CR or TP[n]CR registers of each

active port (a maximum of 16 reads) to determine which port or ports has incurred a COFA. Also via the

Interrupt Enable for Receive COFA (IERC) and Interrupt Enable for Transmit COFA (IETC) control bits

in the RP[n]CR and TP[n]CR registers respectively, the Host can allow/deny the COFA indications to be

passed on to the SRCOFA and STCOFA status bits.

The BERT receiver will report three events, a change in the receive synchronizer status, a bit error being

detected, and if either the Bit Counter or the Error Counter overflows. Each of these events can be

masked within the BERT function via the BERT Control Register (BERTC0). If the software detects that

the BERT has reported an event has occurred, then the software must read the BERT Status Register

(BERTEC0) to determine which event(s) has occurred.

The SM register also reports events as they occur in the PCI Bus and the Local Bus. There are no control

bits to stop these events from being reported in the SM register. When the Local Bus is operated in the

PCI Bridge Mode, SM reports any interrupts detected via the Local Bus LINT* input signal pin and if any

timing errors occur because of the use of the external timing signal LRDY*. When the Local Bus is

operated in the Configuration Mode, the LBINT and LBE bits are meaningless and should be ignored.

SV54 Register

The Status for Receive V.54 Detector (SV54) register reports if the V.54 loopback detector has either

timed out in its search for the V.54 loop up pattern or if the detector has found and verified the loop

up/down pattern. There is a separate status bit (SLBP) for each port. When set, the Host must read the

VTO and VLB status bits in the RP[n]CR register of the corresponding port to find the exact state of the

V.54 detector. When the V.54 detector experiences a time out in it's search for the loop up code (VTO =

1), then the SLBP status bit will be continuously set until the V.54 detector is reset by the Host toggling

the VRST bit in RP[n]CR register. There are no control bits to stop these events from being reported in

the SV54 register. See Figure 4.3.1A for details on the status bits and Section 5 for details on the

operation of the V.54 loopback detector.

SDMA Register

The Status for DMA (SDMA) register reports events that occur regarding the Receive and Transmit DMA

blocks as well as the receive HDLC controller and FIFO. The SDMA will report when the DMA reads

from either the Receive Free Queue or Transmit Pending Queue or writes to the Receive or Transmit

Done Queues. Also reported are error conditions that might occur in the access of one of these queues.

The SDMA will report if any of the HDLC channels experiences a FIFO overflow/underflow condition

and if the receive HDLC controller encounters a CRC error, abort signal, or octet length problem on any

of the HDLC channels.

The Host can determine which specific HDLC channel incurred a FIFO

overflow/underflow, CRC error, octet length error or abort by reading the status bits as reported in Done

Queues which are created by the DMA. There are no control bits to stop these events from being reported

in the SDMA register.

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