DS3134 datasheet(8/203 Pages) DALLAS

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DS3134

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DS3134 FEATURE LIST Table 1A

Layer Can Support Up to 64 T1 or E1 Data Streams or Two T3 Data Streams

One

16 Independent Physical Ports all Capable of Speeds Up to 10 MHz

Two of These Ports are also Capable of Speeds Up to 52 MHz

Each Port can be Independently Configured for Either Channelized or Unchannelized Operation

Each Physical Channelized Port can Handle One, Two, or Four T1 or E1 Data Streams

Supports N x 64 kbps and N x 56 kbps

Onboard V.54 Loopback Detector

Onboard BERT Generation and Detection

Per DS0 Channel Loopback in Both Directions

Unchannelized Loopbacks in Both Directions

HDLC 256 Independent Channels

104 Mbps throughput in both the Receive and Transmit Directions

Transparent Mode

Two Fast HDLC Controllers Capable of Operating Up to 52 MHz

Automatic Flag Detection and Generation

Shared Opening and Closing Flag

Interfame Fill

Zero Stuffing and Destuffing

CRC16/32 Checking and Generation

Abort Detection and Generation

CRC Error and Long/Short Frame Error Detection

Bit Flip

Invert Data

FIFO Large 16 kB Receive and 16 kB Transmit Buffers Maximize PCI Bus Efficiency

Small Block Size of 16 Bytes Allows Maximum Flexibility

Programmable Low and High Water Marks

Programmable HDLC Channel Priority Setting

DMA Efficient Scatter-Gather DMA Minimizes PCI Bus Accesses

Programmable Small and Large Buffer Sizes Up to 8191 Bytes & Algorithm Select

Descriptor Bursting to Conserve PCI Bus Bandwidth

Programmable Packet Storage Address Offset

Identical Receive & Transmit Descriptors Minimize Host Processing in Store-and-Forward

Automatic Channel Disabling and Enabling on Transmit Errors

Receive Packets are Timestamped

Transmit Packet Priority Setting

PCI

32-Bit 33 MHz

Bus

Version 2.1 Compliant

Contains Extension Signals that Allow Adoption to Custom Buses

Can Burst Up to 256 32-Bit Words to Maximize Bus Efficiency

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