DS3134 datasheet(79/203 Pages) DALLAS

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DS3134

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If any of the 256 receive HDLC channels detects an abort sequence, a FCS checksum error, or if the

packet length was incorrect, then the appropriate status bit in the Status Register for DMA (SDMA) will

be set. If enabled, the setting of any of these statuses can cause a hardware interrupt to occur. See

Section 4.3.2 for details on the operation of these status bits.

Receive HDLC Functions Table 6.1B

Zero Destuff

- This operation is disabled if the channel is set to transparent mode.

Flag Detection & Byte Alignment

- Okay to have two packets separated by only one flag or by two flags sharing a zero.

- This operation is disabled if the channel is set to transparent mode.

Octet Length Check

- The minimum check is for 4 bytes with CRC-16 and 6 bytes with CRC-32 (packets with less

than the minimum lengths are not passed to the PCI bus).

- The maximum check is programmable up to 65,536 bytes via the RHPL register.

- The maximum check can be disabled via the ROLD control bit in the RHCD register.

- The minimum and maximum counts include the FCS.

- An error is also reported if a non-integer number of octets occur between flags.

CRC Check

- Can be either set to CRC-16 or CRC-32 or none.

- The CRC can be passed through to the PCI bus or not

- The CRC check is disabled if the channel is set to transparent mode.

Abort Detection

- Checks for seven or more ones in a row.

Invert Data

- All data (including the flags & FCS) is inverted before HDLC processing.

- Also available in the transparent mode.

Bit Flip

- The first bit received becomes either the LSB (normal mode) or the MSB (telecom mode) of the

byte stored in the FIFO.

- Also available in the transparent mode.

Transparent Mode

- If enabled, flag detection, zero destuffing, abort detection, length checking, and FCS checking

are disabled.

- Data is passed to the PCI Bus on octet (i.e. byte) boundaries in channelized operation.

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