DS3134 datasheet(10/203 Pages) DALLAS

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DS3134

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DATA SHEET DEFINITIONS Table 1B

Acronym

Or Term

Definition

BERT

Bit Error Rate Tester.

Descriptor

A message passed back and forth between the DMA and the Host.

Dword

Double Word. A 32-bit data entity.

DMA

Direct Memory Access.

FIFO

First In First Out. Temporary memory storage scheme.

HDLC

High level Data Link Control.

Host

The main controller that resides on the PCI Bus.

n/a

Not Assigned.

V.54

A pseudorandom pattern used to control loopbacks (see ANSI T1.403)

GOVERNING SPECIFICATIONS Table 1C

ANSI (American National Standards Institute) T1.403-1995 Network-to-Customer Installation DS1

Metallic Interface March 21, 1995.

PCI Local Bus Specification V2.1 June 1, 1995.

GENERAL DESCRIPTION

The Layer One Block handles the physical input and output of serial data to and from the DS3134. The

DS3134 is capable of handling up to 64 T1 or E1 data streams or 2 T3 data streams. Each of the 16

physical ports can handle up to two or four T1 or E1 data streams. Section 14 contains some examples of

how this is performed. The Layer One Block prepares the incoming data for the HDLC Block and grooms

data from the HDLC Block for transmission. The block has the ability to perform both channelized and

unchannelized loopbacks as well as search for V.54 loop patterns. It is in the Layer One Block that the

Host will enable HDLC channels and assign them to a particular port and/or DS0 channel(s). The Host

assigns HDLC channels via the R[n]CFG[j] and T[n]CFG[j] registers, which are described in Section 5.3.

The Layer One Block interfaces directly to the Bit Error Rate Tester (BERT) Block. The BERT Block

can generate and detect both pseudorandom and repeating bit patterns and it is used to test and stress data

communication links.

The HDLC Block consists of two types of HDLC controllers. There are 16 Slow HDLC Engines (one for

each port) that are capable of operating at speeds up to 8.192 Mbps in channelized mode and up to

10 Mbps in unchannelized mode. There are also two Fast HDLC Engines, which only reside on Ports 0

and 1 and they are capable of operating at speeds up to 52 Mbps. Via the RP[n]CR and TP[n]CR

registers in the Layer One Block, the Host will configure Port 0 and 1 to use either the Slow or the Fast

HDLC engine. The HDLC Engines perform all of the Layer 2 processing which include, zero stuffing

and destuffing, flag generation and detection, CRC generation and checking, abort generation and

checking.

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