DS3134 datasheet(25/203 Pages) DALLAS

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DS3134

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Signal Name:

LA0 to LA19

Signal Description:

Local Bus Non-Multiplexed Address Bus

Signal Type:

Input / Output (tri-state capable)

In the PCI Bridge Mode (LMS = 0), these signals are outputs that will be asserted on the rising edge of

LCLK to indicate which address to be written to or read from. These signals will be tri-stated when the

Local Bus is not currently involved in a bus transaction and driven when a bus transaction is active. In the

Configuration Mode (LMS = 1), these signals are inputs and only the bottom 16 (LA[15:0]) are active, the

upper four (LA[19:16]) are ignored and should be tied low. These signals will be sampled on the rising

edge of LCLK to determine the internal device configuration register that the external host wishes to

access.

Signal Name:

LWR* (LR/W*)

Signal Description:

Local Bus Write Enable (Local Bus Read/Write Select)

Signal Type:

Input / Output (tri-state capable)

In the PCI Bridge Mode (LMS = 0), this output signal is asserted on the rising edge of LCLK. In Intel

Mode (LIM = 0) it will be asserted when data is to be written to the Local Bus. In Motorola Mode (LIM

= 1), this signal will determine whether a read or write is to occur. If bus arbitration is enabled via the

Local Bus Arbitration (LARBE) control bit in the Local Bus Bridge Mode Control Register (LBBMC),

then this signal will be tri-stated when the Local Bus is not currently involved in a bus transaction and

driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. In

the Configuration Mode (LMS = 1), this signal is sampled on the rising edge of LCLK. In Intel Mode

(LIM = 0) it will determine when data is to be written to the device. In Motorola Mode (LIM = 1), this

signal will be used to determine whether a read or write is to occur.

Signal Name:

LRD* (LDS*)

Signal Description:

Local Bus Read Enable (Local Bus Data Strobe)

Signal Type:

Input / Output (tri-state capable)

In the PCI Bridge Mode (LMS = 0), this active low output signal is asserted on the rising edge of LCLK.

In Intel Mode (LIM = 0) it will be asserted when data is to be read from the Local Bus. In Motorola Mode

(LIM = 1), the rising edge will be used to write data into the slave device. If bus arbitration is enabled via

the Local Bus Arbitration (LARBE) control bit in the Local Bus Bridge Mode Control Register

(LBBMC), then this signal will be tri-stated when the Local Bus is not currently involved in a bus

transaction and driven when a bus transaction is active. When bus arbitration is disabled, this signal is

always driven. In the Configuration Mode (LMS = 1), this signal is an active low input which is sampled

on the rising edge of LCLK. In Intel Mode (LIM = 0) it will determine when data is to be read from the

device. In Motorola Mode (LIM = 1), the rising edge will be used to write data into the device.

Signal Name:

LINT*

Signal Description:

Local Bus Interrupt

Signal Type:

Input / Output (open drain)

In the PCI Bridge Mode (LMS = 0), this active low signal is an input which sampled on the rising edge of

LCLK. If asserted and unmasked, this signal will cause an interrupt at the PCI bus via the PINTA*

signal. If not used in the PCI Bridge Mode, this signal should be tied high. In the Configuration Mode

(LMS = 1) this signal is an open drain output which will be forced low if one or more unmasked interrupt

sources within the device is active. The signal will remain low until the interrupt is either serviced or

masked.

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