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DS3134

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Signal Description:

PCI Bus Parity

Signal Type:

Input / Output (tri-state capable)

This signal provides information on even parity across both the PAD address/data bus and the PCBE bus

command/byte enable bus. When the device is an initiator, this signal is an output for writes and input for

reads and is updated on the rising edge of PCLK. When the device is a target, this signal is input for

writes and an output for reads and is sampled on the rising edge of PCLK. When the device is not

involved in a bus transaction, PPAR is tri-stated.

Signal Name:

PFRAME*

Signal Description:

PCI Cycle Frame

Signal Type:

Input / Output (tri-state capable)

This active low signal is created by the bus initiator and is used to indicate the beginning and duration of a

bus transaction. PFRAME* is asserted by the initiator during the first clock cycle of a bus transaction and

it will remain asserted until the last data phase of a bus transaction. When the device is an initiator, this

signal is an output and is updated on the rising edge of PCLK. When the device is a target, this signal is

input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction,

PFRAME* is tri-stated.

Signal Name:

PIRDY*

Signal Description:

PCI Initiator Ready

Signal Type:

Input / Output (tri-state capable)

This active low signal is created by the initiator to signal the target that it is ready to send/accept or to

continue sending/accepting data.

This signal handshakes with the PTRDY* signal during a bus

transaction to control the rate at which data transfers across the bus. During a bus transaction, PIRDY* is

deasserted when the initiator cannot temporarily accept or send data and a wait state is invoked. When the

device is an initiator, this signal is an output and is updated on the rising edge of PCLK. When the device

is a target, this signal is input and is sampled on the rising edge of PCLK. When the device is not

involved in a bus transaction, PIRDY* is tri-stated.

Signal Name:

PTRDY*

Signal Description:

PCI Target Ready

Signal Type:

Input / Output (tri-state capable)

This active low signal is created by the target to signal the initiator that it is ready to send/accept or to

continue sending/accepting data. This signal handshakes with the PIRDY* signal during a bus transaction

to control the rate at which data transfers across the bus. During a bus transaction, PTRDY* is deasserted

when the target cannot temporarily accept or send data and a wait state is invoked. When the device is a

target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator,

this signal is input and is sampled on the rising edge of PCLK. When the device is not involved in a bus

transaction, PTRDY* is tri-stated.

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