DS3134 datasheet(30/203 Pages) DALLAS

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DS3134

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Signal Name:

PSTOP*

Signal Description:

PCI Stop

Signal Type:

Input / Output (tri-state capable)

This active low signal is created by the target to signal to the initiator that it requests the initiator stop the

current bus transaction. When the device is a target, this signal is an output and is updated on the rising

edge of PCLK. When the device is an initiator, this signal is input and is sampled on the rising edge of

PCLK. When the device is not involved in a bus transaction, PSTOP* is tri-stated.

Signal Name:

PIDSEL

Signal Description:

PCI Initialization Device Select

Signal Type:

Input

This input signal is used as a chip select during configuration read and writes transactions. This signal is

disabled when the Local Bus is set in the Configuration Mode (LMS = 1). When PIDSEL is set high

during the address phase of a bus transaction and the Bus Command signals (PCBE0 to PCBE3) indicate

a register read or write, then the device allows access to the PCI configuration registers and the

PDEVSEL* signal is asserted during the PCLK cycle. PIDSEL is sampled on the rising edge of PCLK.

Signal Name:

PDEVSEL*

Signal Description:

PCI Device Select

Signal Type:

Input / Output (tri-state capable)

This active low signal is created by the target when it has decoded the address sent to it by the initiator, as

it's own to indicate that that the address is valid. If the device is an initiator and does not see the signal

asserted within six PCLK cycles, then the bus transaction is aborted and the PCI Host is alerted. When the

device is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is

an initiator, this signal is input and is sampled on the rising edge of PCLK. When the device is not

involved in a bus transaction, PDEVSEL* is tri-stated.

Signal Name:

PREQ*

Signal Description:

PCI Bus Request

Signal Type:

Output (tri-state capable)

This active low signal is asserted by the initiator to request that the PCI bus arbiter allow it access to the

bus. PREQ* is updated on the rising edge of PCLK.

Signal Name:

PGNT*

Signal Description:

PCI Bus Grant

Signal Type:

Input

This active low signal is asserted by the PCI bus arbiter to indicate to the PCI requesting agent that access

to the PCI bus has been granted. The device samples PGNT* on the rising edge of PCLK and if detected,

will initiate a bus transaction when it has sensed that the PFRAME* signal has been deasserted.

Signal Name:

PPERR*

Signal Description:

PCI Parity Error

Signal Type:

Input / Output (tri-state capable)

This active low signal reports parity errors that occur. PPERR* can be enabled and disabled via the PCI

Configuration Registers. This signal is updated on the rising edge of PCLK.

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