DS3134 datasheet(14/203 Pages) DALLAS

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DS3134

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INITIALIZATION

On a system reset (which can be invoked by either hardware action via the PRST* signal or software

action via the RST control bit in the Master Reset and ID register), all of the internal device configuration

not affected by software invoked system reset, it will be forced to all zeros only by hardware reset. The

internal registers within that are accessed indirectly (these are listed as "indirect registers" in the data

sheet and consist of the Channelized Port registers in the Layer One Block, the DMA Configuration

RAMs, the HDLC Configuration registers, and the FIFO registers) are not affected by a system reset and

they must be configured on power-up by the Host to a proper state. Figure 1B lists the ordered steps to

initialize the DS3134.

Note:

After device power up and reset, it takes 0.625 mS to get a port up and operating. In other words, the

ports must have wait a minimum of 0.625 mS before packet data can be processed.

INITIALIZATION STEPS Figure 1B

Initialization Step

Comments

1. Initialize the PCI Configuration

Registers

Achieved by asserting the PIDSEL signal.

2. Initialize All Indirect Registers

It is recommended that all of the indirect

registers be set to 0000h. See Table 1E.

3. Configure the Device for Operation

Program all the necessary registers, which

includes the Layer One, HDLC, FIFO, and

DMA registers.

4. Enable the HDLC Channels

Done via the RCHEN and TCHEN bits in

the R[n]CFG[j] and T[n]CFG[j] registers.

5. Load the DMA Descriptors

Indicate to the DMA where packet data can

be written and where pending data (if any)

resides

6. Enable the DMAs

Done via the RDE and TDE control bits in

the Master Configuration (MC) register.

7. Enable DMA for each HDLC Channel

Done via the Channel Enable bit in the

Receive & Transmit Configuration RAM

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