82374EB datasheet(67/208 Pages) INTEL

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82374EB82374SB

Bit

Description

232

Upper Mid Lower Stop Bits

These 22 bits provide the Stop Address If the Stop function is

enabled then the channel will Stop whenever its Memory Address matches the Stop Address

Bits 2316 are the upper stop bits Bits 158 are the mid stop bits and bits 72 are the lower stop

bits Bits 10 are not used and are don’t cares

3217 CHAINCHAINING MODE REGISTER

040AhChannels 0-3

04D4hChannels 4-7

Default Value

000000xxb

Attribute

Write Only

Size

8 Bits

Each channel has a Chaining Mode register The Chaining Mode register enables or disables DMA buffer

chaining and indicates when the DMA Base registers are being programmed When writing to the register

bits 10 determine which channel’s Chaining Mode register to program The chaining status and interrupt

status for all channels can be determined by reading the Chaining Mode Status Channel Interrupt Status and

Chain Buffer Expiration Control registers The Chaining Mode register is reset to zero upon reset access (read

or write) of a channel’s Mode register or Extended Mode register or a Master Clear The values upon reset are

disable chaining mode and generate IRQ13

Bit

Description

Reserved

Must be 0

Buffer Expired Signal

After one of the two buffers in the DMA expires then the DMA will inform the

CPU that the next buffer should be loaded into the base register set This bit determines whether

IRQ13 or EOP should be used to inform the CPU that the buffer is complete 1egenerate TC

0eGenerate IRQ13 1eProgramming complete 0eDon’t start chaining

Base Register Programming

After the reserve buffer’s address and word count are written to the

base register set this bit should be set to 1 to inform the DMA that the second buffer is ready for

transfer

Buffer Chaining Mode

Bit 2 enables the chaining mode logic If the bit is set to 1 after the initial DMA

address and word count are programmed then the Base address and word count are available for

programming the next buffer in the chain 1eEnable chaining 0eDisable chaining

DMA Channel Select

Bits 10 select the DMA channel mode register to program with bits 42

Bits 10

Channel

0or4

1or5

2or6

3or7

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