82374EB datasheet(49/208 Pages) INTEL

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82374EB82374SB

Bit

Description

IRQ4 SMI Enable (COM2COM4 Interrupt or Mouse)

Thsi bit enables the IRQ4 signal to generate

an SMI When bit 1e1 asserting the IRQ3 input signal generates an SMI When bit 2e0 asserting

IRQ4 does not generate an SMI

IRQ3 SMI Enable (COM1COM3 Interrupt or Mouse)

This bit enables the IRQ3 signal to generate

an SMI When bit 1e1 asserting the IRQ3 input signal generates an SMI When bit 1e0 asserting

IRQ3 does not generate an SMI

IRQ1 SMI Enable (Keyboard Interrupt)

This bit enables the IRQ1 signal to generate an SMI When

bit 0e1 asserting the IRQ1 input signal generates an SMI When bit 0e0 asserting IRQ1 does not

generate an SMI

3121 SEESYSTEM EVENT ENABLE REGISTER

Address Offset

A4-A7h

Default Value

00000000h

Attribute

ReadWrite

Size

32 Bits

For the 82374SB this register enables hardware events as system events or break events for power manage-

ment control Note that all of the functional bits in the SEE Register provide system event control In addition

all bits also provide break event control The default for each systembreak event in this register is disabled

System events

Activity by these events can keep the system from powering down When a system event is

enabled the corresponding hardware event activity prevents a Fast Off powerdown condition Anytime the

corresponding hardware event occurs (signal is asserted) the Fast Off Timer is re-loaded with its initial count

Break events

These events can awaken a powered down system When a break event is enabled the

corresponding hardware event activity powers up the system by negating STPCLK

Note that STPCLK

not negated until the stop grant special cycle has been generated by the CPU Thus from the time that

STPCLK

is asserted until the stop grant cycle is returned the occurrence of subsequent break events are

latched in the ESC

NOTE

INIT is always enabled as a break event However INIT only causes a break event after a stop grant

special cycle has been received If INIT is asserted while STPCLK

is active and then negated be-

fore the stop grant cycle is received INIT does not cause a break event

Bit

Description

Fast Off SMI Enable (FSMIEN)

When bit 31e1 (enabled) an SMI causes a system event that re-

loads the Fast Off Timer and a break event that negates the STPCLK

signal When bit 31e0

(disabled) an SMI does not re-load the Fast Off Timer or negate the STPCLK

signal

Reserved

Fast Off NMI Enable (FNMIEN)

When bit 29e1 (enabled) an NMI (eg parity error) causes a system

event that re-loads the Fast Off Timer and a break event that negates the STPCLK

signal When bit

29e0 (disabled) an SMI does not re-load the Fast Off Timer or negate the STPCLK

signal

82374EB Folha de dados(PDF) 49 Page - Intel Corporation

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