82374EB datasheet(89/208 Pages) INTEL

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82374EB82374SB

3412 NMIESCNMI EXTENDED STATUS AND CONTROL REGISTER

0461h

Default Value

See below

Attribute

ReadWrite Read Only

Size

8 Bits

This register is used to check the status of different system components control the output of the Speaker

Counter (Timer 1 Counter 2) and gate the counter output that drives the SPKR signal

Bits 4 5 6 and 7 are read-only Bits 0-3 are both read and write When writing to this port these bits must be

written as 0’s Bit 7 returns the Fail-Safe Timer Status This input comes from Timer 2 Counter 0 The current

status of bit 2 enables or disables this Fail-Safe Timer NMI source Bit 6 returns the Bus Timeout Status Bit 6

is set if either a 64 BCLK or a 256 BCLK occurs The current status of bit 3 enables or disables this Fail-Safe

Timer NMI source If NMI is caused by a Bus Timeout bit 4 distinguished between the 8 ms (64 BCLK) and

32 ms (256 BCLK) timeout Bit 5 is the current state of an IO write to port 0462h The current status of bit 1

enables or disables Software generated NMI Bit 0 controls the state of the RSTDRV output signal If bit 0 is

set to 1 the RSTDRV signal is asserted and a system bus reset is performed Bit 0 should be set long enough

(l 8 BCLKs) for the system bus devices to be properly reset

Bit

Description

Fail-Safe Timer StatusRO

This bit indicates the status of the Fail-safe Timer When Timer 2

Counter 0 count expires this bit is set toa1ifbit2has previously been set to 1 A value of 0 indicates

that the current NMI was not caused by the Fail-Safe Timer A value of 1 indicates that the Fail-Safe

timer has timed out

Bus Timeout StatusRO

This bit indicates the status of Bus master timeout logic If this bit is 0 the

Bus Master timeout logic has not detected a bus timeout If this bit is 1 the bus master timeout logic

has detected a bus timeout

Software NMI StatusRO

This bit indicates the status of the Software NMI port writes A write to IO

port 0462 of any value will set this bit to 1 if bit 1 is set to 1 If this bit is 0 the current NMI was not

caused by a write to the NMI Port If this bit is 1 the current NMI was caused by a write to the NMI Port

Bus Timeout StatusRO

This bit indicates the status of the 8 ms EISA Bus master timeout event If

the bit is 0 the current NMI was not caused by the 8 ms EISA bus master timeout If this bit is 1 the

current NMI was caused by this bus timeout

Bus Timeout EnableRW

This bit enablesdisables NMI EISA bus timeout If this bit is 0 an NMI

will not be generated for bus timeout Also the NMI condition caused by the Bus timeout will be

cleared If this bit is 1 an NMI will be generated when Timer 2 Counter 0 count expires

Fail-Safe NMI EnableRW

This bit enablesdisables NMI when the Fail-Safe Timer timesout If this

bit is 0 an NMI will not be generated when the Timer 2 Counter 0 count expires Also the NMI condition

caused by the Fail-Safe Timer will be cleared If this bit is 1 an NMI will be generated when Timer 2

Counter 0 count expires

Software NMI EnableRW

This bit enablesdisables software generated NMI If this bit is 0 a write

to IO port 0462h will not generate an NMI If this bit is 1 NMI will be generated for a write to IO port

0462h

Bus ResetRW

When bit 0 is a 0 RSTDRV signal function as a normal reset drive signal When bit

0 is 1 the RSTDRV signal is asserted Following reset bit 0 is a 0 and the RSTDRV output is low

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