82374EB datasheet(56/208 Pages) INTEL

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82374EB82374SB

Bit

Description

DMA Cycle Timing Mode

The ESC supports four DMA transfer timings ISA-compatible Type A

Type B and Burst Each timing and its corresponding code are described below Upon reset

compatible timing is selected and the value of these bits is ‘‘00’’ The cycle timings noted below are for

a BCLK (833 MHz maximum BCLK frequency) DMA cycles to ISA expansion bus memory will default

to compatible timing if the channel is programmed in one of the performance timing modes (Type A B

or Burst)

Compatible Timing

DMA slaves on the ISA bus may run compatible DMA cycles Bits 54 must be programmed to 00

Compatible timing is provided for DMA slave devices which due to some design limitation cannot

support one of the faster timings Compatible timing runs at 9 BCLKs (1080 nssingle cycle) and 8

BCLKs (960 nscycle) during the repeated portion of a BLOCK or DEMAND mode transfers

Type ‘‘A’’ Timing

Type ‘‘A’’ timing is provided to allow shorter cycles to EISA memory If ISA memory is decoded the

system automatically reverts to ISA DMA type compatible timing on a cycle-by-cycle basis Type ‘‘A’’

timing runs at 7 BCLKs (840 nssingle cycle) and 6 BCLKs (720 nscycle) during the repeated portion

of a BLOCK or DEMAND mode transfer Type ‘‘A’’ timing varies from compatible timing primarily in

shortening the memory operation to the minimum allowed by system memory The IO portion of the

cycle (data setup on write IO read access time) is the same as with compatible cycles The actual

active command time is shorter but it is expected that the DMA devices which provide the data access

time or write data setup time should not require excess IOR

or IOW

command active time

Because of this most ISA DMA devices should be able to use type ‘‘A’’ timing

Type ‘‘B’’ Timing

Type ‘‘B’’ timing is provided for 8-16- bit ISA or EISA DMA devices which can accept faster IO

timing Type ‘‘B’’ only works with EISA memory Type ‘‘B’’ timing runs at 6 BCLKs (720 nssingle

cycle) and 4 BCLKs (480 nscycle) during the repeated portion of a BLOCK or DEMAND mode

transfer Type ‘‘B’’ timing requires faster DMA slave devices than compatible timing in that the cycles

are shortened so that the data setup time on IO write cycles is shortened and the IO read access

time is required to be faster Some of the current ISA devices should be able to support type ‘‘B’’

timing but these will probably be more recent designs using relatively fast technology

Type ‘‘C’’ Timing (Burst)

Burst timing is provided for high performance EISA DMA devices The DMA slave device needs to

monitor the EXRDY and IORC

or IOWC

signals to determine when to change the data (on writes)

or sample the data (on reads) This timing will allow up to 33 MBytes per second transfer rate with a

32-bit DMA device and 32-bit memory Note that 8- or 16-bit DMA devices are supported (through the

programmable Address size) and that they use the ‘‘byte lanes’’ natural to their size for the data

transfer As with all bursts the system will revert to two BCLK cycles if the memory does not support

burst When a DMA burst cycle accesses non-burst memory and the DMA cycle crosses a page

boundary into burstable memory the ESC will continue performing non-burst cycles This will not

cause a problem since the data is still transferred correctly

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