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82374EB Folha de dados(PDF) 46 Page - Intel Corporation |
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82374EB Folha de dados(HTML) 46 Page - Intel Corporation |
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46 / 208 page ![]() 82374EB82374SB 3115 GPCSM 20 GENERAL PURPOSE CHIP SELECT MASK REGISTER Address Offset 66h 6Ah 6Eh Default Value 00h Attribute ReadWrite Size 8 Bits This register contains the mask bits for determining the address range for which the GPCSx signals are generated If a register bit is set to a 1 then the corresponding bit in the GPCSL register is not compared with the address signal in the generation of the GPCSx signals If Mode Select Register (offset 40h) bit 4e1 offset register 6Eh is ignored Bit Description 70 GPCS Mask Register The contents of these bits are used to determine which bits to compare GPCSLA 20 with the address lines LA 70 A 1 bit means the bit should not be compared 3116 GPXBCGENERAL PURPOSE PERIPHERAL X-BUS CONTROL REGISTER Address Offset 6Fh Default Value xxxx x000b Attribute ReadWrite Size 8 Bits The register controls the generation of the X-BUS buffer output enable (XBUSOE ) signal for IO accesses to the peripherals mapped in the General Purpose Chip Select address decode range This register determines if the General Purpose Peripheral is placed on the XBUS or not If the General Purpose Peripheral is on the X-Bus then the corresponding bit is set to 1 Otherwise the bit is set to 0 Bit Description 73 Reserved 2 XBUSOE Generation for GPCS2 When this bit is enabled XBUSOE will be generated when GPCS2 is generated 1eEnabled 0eDisabled 1 XBUSOE Generation for GPCS1 When this bit is enabled XBUSOE will be generated when GPCS1 is generated 1eEnabled 0eDisabled 0 XBUSOE Generation for GPCS0 When this bit is enabled XBUSOE will be generated when GPCS0 is generated1eEnabled 0eDisabled 46 |
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