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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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82374EB Folha de dados(PDF) 45 Page - Intel Corporation |
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82374EB Folha de dados(HTML) 45 Page - Intel Corporation |
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45 / 208 page  82374EB82374SB Bit Description 7 Routing of Interrupts When enabled (0) this bit routes the PCI Interrupt signal to the PC compatible interrupt signal specified in bits 60 After a reset or a power-on this bit is disabled (set to 1) 60 IRQx Routing Bits These bits specify which IRQ signal to generate when the PCI Interrupt for this register has been triggered Bits 60 IRQx Bits 60 IRQx 0000000 Reserved 0001001 IRQ9 0000001 Reserved 0001010 IRQ10 0000010 Reserved 0001011 IRQ11 0000011 IRQ3 0001100 IRQ12 0000100 IRQ4 0001101 Reserved 0000101 IRQ5 0001110 IRQ14 0000110 IRQ6 0001111 IRQ15 0000111 IRQ7 0010000 to 0001000 Reserved 1111111 Reserved 3113 GPCSLA 20 GENERAL PURPOSE CHIP SELECT LOW ADDRESS REGISTER Address Offset 64h 68h 6Ch Default Value 00h Attribute ReadWrite Size 8 Bits This register contains the low byte of the General Purpose Peripheral mapping address The contents of this register are compared with the LA 70 address lines The contents of this register the GPCSHA Register and the GPCSM Register control the generation the GPCS 20 signal or the ESC 20 signal (101 110 combina- tion) If Mode Select Register (offset 40h) bit 4e1 offset register 6Ch is ignored Bit Description 70 GPCS Low Address Byte The contents of these bits are compared with the address lines LA 70 to generate the GPCS 20 signal or the ECS 20 combination for this register The mask register (GPCSM 20 ) determines which bits to use during the comparison 3114 GPCSHA 20 GENERAL PURPOSE CHIP SELECT HIGH ADDRESS REGISTER Address Offset 65h 69h 6Dh Default Value C0h Attribute ReadWrite Size 8 Bits This register contains the high byte of the General Purpose Peripheral mapping address The contents of this register are compared with the LA 158 address lines The contents of this register the GPCSLA Register and the GPCSM Register control the generation the GPCS 20 signal or the ESC 20 signal (101 110 combina- tion) If Mode Select Register (offset 40h) bit 4e1 offset register 6Dh is ignored Bit Description 70 GPCS High Address Byte The contents of these bits are compared with the address lines LA 158 to generate the GPCS 20 signal or the ECS 20 combination for this register 45 |
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