82374EB datasheet(96/208 Pages) INTEL

96 / 208 page

82374EB82374SB

Bit

Description

6356

Destination Field

If the Destination Mode of this entry is Physical Mode (bit 11e0) bits 5956

contain an APIC ID If Logical Mode is selected (bit 11e1) the Destination Field potentially defines

a set of processors Bits 6356 of the Destination Field specify the logical destination address

5517

Reserved

Interrupt Mask

When this bit is 1 the interrupt signal is masked Edge-sensitive interrupts signaled

on a masked interrupt pin are ignored (ie not delivered or held pending) Level-asserts or negates

occurring on a masked level-sensitive pin are also ignored and have no side effects Changing the

mask bit from unmasked to masked after the interrupt is accepted by a local APIC has no effect on

that interrupt This behavior is identical to the case where the device withdraws the interrupt before

that interrupt is posted to the processor It is software’s responsibility to handle the case where the

mask bit is set after the interrupt message has been accepted by a local APIC unit but before the

interrupt is dispensed to the processor When this bit is 0 the interrupt is not masked An edge or

level on an interrupt pin that is not masked results in the delivery of the interrupt to the destination

Trigger ModeRW

The trigger mode field indicates the type of signal on the interrupt pin that

triggers an interrupt This bit is set to 1 for level sensitive and 0 for edge sensitive

Remote IRRRO

This bit is used for level triggered interrupts Its meaning is undefined for edge

triggered interrupts For level triggered interrupts this bit is set to 1 when local APIC(s) accept the

level interrupt sent by the IO APIC The Remote IRR bit is set to 0 when an EOI message with a

matching interrupt vector is received from a local APIC

Interrupt Input Pin Polarity (INTPOL)RW

This bit specifies the polarity of the interrupt signal

A 0 selects high active and a 1 selects low active

Delivery Status (DELIVS)RO

The Delivery Status bit contains the current status of the delivery

of this interrupt Delivery Status is read-only and writes to this bit (as part of a 32 bit word) do not

effect this bit When bit 12e0 (IDLE) there is currently no activity for this interrupt When bit 12e1

(Send Pending) the interrupt has been injected However its delivery is temporarily held up due to

the APIC bus being busy or the inability of the receiving APIC unit to accept that interrupt at that

time

Destination Mode (DESTMOD)RW

This field determines the interpretation of the Destination

field When DESTMODe0 (physical mode) a destination APIC is identified by its ID Bits 56 through

59 of the Destination field specify the 4 bit APIC ID When DESTMODe1 (logical mode)

destinations are identified by matching on the logical destination under the control of the Destination

Format Register and Logical Destination Register in each Local APIC Bits 56 through 63 (8 MSB) of

the Destination field specify the 8 bit APIC ID

82374EB Folha de dados(PDF) 96 Page - Intel Corporation

82374EB Folha de dados(HTML) 96 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL