82374EB datasheet(35/208 Pages) INTEL

35 / 208 page

82374EB82374SB

212 Test Signal

Pin Name

Type

Description

INITTEST

TEST

On the 82374EB this pin only functions as a TEST pin

On the 82374SB the function of this pin is selected by the value on the GPCS0

at reset If GPCS0

is low INIT is selected and if GPCS0

is high TEST is selected

INIT

For INIT signal description see the Power Management Signal section

TEST

TEST is used to tri-state all of the outputs For normal operations this signal should be

tied to VCC For test mode this pin should be tied to ground

30 REGISTER DESCRIPTION

The ESC contains ESC configuration registers DMA registers Timer Unit registers Interrupt Unit registers

and EISA configuration registers All of the registers are accessible from the EISA bus During a reset the ESC

sets its internal registers to predetermined default states The default values are indicated in the individual

The following notation is used to describe register access attributes

Read Only

If a register is read only writes have no effect

Write Only

If a register is write only reads have no effect

ReadWrite

A register with this attribute can be read and written Note that individual bits in some

readwrite registers may be read only

31 Configuration Registers

The ESC’s configuration registers are accessed through an indexing scheme The index address register is

located at IO address 0022h and the index data register is located at IO address 0023h The offset (data)

written into the index address register selects the desired configuration register Data for the selected configu-

ration register can be read from or written to by performing a read or a write to the index data register See the

Address Decode section for a summary of configuration register index addresses

Some of the ESC registers described in this section contain reserved bits These bits are labeled ‘‘R’’ Soft-

ware must deal correctly with fields that are reserved On reads software must use appropriate masks to

extract the defined bits and not rely on reserved bits being any particular value On writes software must

ensure that the values of reserved bit positions are preserved That is the values of reserved bit positions

must first be read merged with the new values for other bit positions and then written back

In addition to reserved bits within a register the ESC’s configuration space contains address locations that are

marked ‘‘Reserved’’ (See Address Decode Section) The ESC responds to accesses to these address loca-

tions by completing the Host cycle When a reserved register location is read 0000h is returned Writes to

reserved registers have no effect on the ESC

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