82374EB datasheet(21/208 Pages) INTEL

21 / 208 page

82374EB82374SB

Pin Name

Type

Description

MSBURST

MASTER BURST

MSBURST

signal is asserted by an EISA master to indicate

EISA burst cycles MSBURST

is asserted by an EISA master in response to an

asserted SLBURST

signal The ESC samples SLBURST

on the rising edge of

BCLK that CMD

is asserted If asserted the ESC samples SLBURST

on all

subsequent rising edges of BCLK until sampled negated The ESC keeps CMD

asserted during Burst cycles MSBURST

is an output during DMA burst cycles

The ESC drives MSBURST

active on the falling edge of BCLK one half BCLK

after SLBURST

is sampled active at the end of START

MASTER16

MASTER 16-BIT

MASTER16

is asserted by a 16-bit EISA Bus master or an ISA

Bus master device to indicate that it has control of the EISA Bus or ISA Bus The

ESC samples MASTER16

on the rising edge of BCLK that START

is asserted If

MASTER16

is sampled asserted the ESC determines that a 16-bit EISA Bus

master or an ISA Bus master owns the Bus If MASTER16

is sampled negated at

the first sampling point the ESC will sample MASTER16

a second time on the

rising edge of BCLK at the end of START

If MASTER16

is sampled asserted

here the ESC determines that a 32-bit EISA Bus master has downshifted to a 16-bit

Bus master and thus the ESC will disable the data size translation function

SD 70

SYSTEM DATA

SD 70 signals are directly connected to the System Data bus

The SD 70 pins are outputs during IO reads when the ESC internal registers are

being accessed and during interrupt acknowledge cycles The SD 70 pins are

input during IO writes cycles when the ESC internal registers are being accessed

23 ISA Bus Signals

Pin Name

Type

Description

BALE

out

BUS ADDRESS LATCH ENABLE

BALE signal is asserted by the ESC to indicate that

a address (SA 190 LA 2317 ) AEN and SBHE

signal lines are valid The

LA 2317 address lines are latched on the trailing edge of BALE BALE remains active

throughout DMA and ISA Master cycles and Refresh cycles

SA 10

ISA ADDRESS BITS 0

SA 10 are the least significant bits of the ISA address bus

SA 10 are inputs to the ESC during ISA master cycles except during ISA master

initiated Refresh cycles The ESC uses the SA 10 in conjunction with SBHE

generate BE 30

on the EISA bus The SA 10 are outputs of the ESC during EISA

master cycles and DMA cycles The ESC generates these from BE 30

SBHE

ISA BYTE HIGH ENABLE

SBHE

signal indicates that the high byte on the ISA data

bus (SD 158 ) is valid SBHE

is an input to the ESC during ISA master cycles except

during ISA master initiated Refresh cycles The ESC uses the SBHE

in conjunction

with SA 10 to generate BE 30

on the EISA bus SBHE

is an output during EISA

master and DMA cycles

82374EB Folha de dados(PDF) 21 Page - Intel Corporation

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