82374EB datasheet(33/208 Pages) INTEL

33 / 208 page

82374EB82374SB

Pin Name

Type

Description

DLIGHT

out

FIXED DISK ACTIVITY LIghtPCI INTERRUPT REQUEST 0

This signal has two

functions depending on the programming of the Mode Select Register As DLIGHT

PIRQ0

this signal controls the fixed disk X light When low the light is on When high the light

is off If either bit 6 or bit 7 of the Port 92 register is set to a 1 (bit 6 and 7 are internally

NOR’ed together) DLIGHT

is driven active (low) Setting both bits 6 and 7 low will

cause DLIGHT

to be driven high For the PIRQ0

function see the Mode Select

function an external pull-up resistor

(10 KX –20 KX) must be added to this signal

2117 CONFIGURATION RAM INTERFACE

Pin Name

Type

Description

CRAMRD

out

CONFIGURATION RAM READ COMMAND

CRAMRD

is connected directly to the

system Configuration RAM The ESC asserts CRAMRD

for IO reads from the

address range programmed into the low and high bytes of the configuration RAM

command registers

CRAMWR

out

CONFIGURATION RAM WRITE COMMAND

This is an active Low output

CRAMWR

is connected directly to the system Configuration RAM The ESC

activates CRAMWR

for IO writes to the address range programmed into the low

and high bytes of the configuration RAM command registers

2118 X-BUS CONTROL AND GENERAL PURPOSE DECODE

Pin Name

Type

Description

XBUSTR

out

X-BUS DATA TRANSMITRECEIVE

XBUSTR

is tied directly to the direction

control of a 74F245 that buffers the X-Bus data XD(70) from the system data bus

SD(70) XBUSTR

is driven high (transmit) during IO and memory reads for EISA

and ISA masters For DMA cycles (channel 2 only) XBUSTR

is driven high for the

following cases

1 Memory read IO write cycles where LBIOSCS

is asserted

2 IO read memory write cycles where Digital Output Register bit 3 is set to 1

XBUSTR

is driven low (receive) under all other conditions

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