82374EB datasheet(17/208 Pages) INTEL

17 / 208 page

82374EB82374SB

Advanced Programmable Interrupt Controller (APIC)

In addition to the standard EISA compatible interrupt controller described above the ESC incorporates the

Advanced Programmable Interrupt Controller (APIC) While the standard interrupt controller is intended for use

in a uni-processor system APIC can be used in either a uni-processor or multi-processor system APIC

provides multi-processor interrupt management and incorporates both static and dynamic symmetric interrupt

distribution across all processors In systems with multiple IO subsystems each subsystem can have its own

set of interrupts

TimerCounter

The ESC provides two 82C54 compatible timers (Timer 1 and Timer 2) The counters in Timer 1 support the

system timer interrupt (IRQ0 ) refresh request and a speaker tone output (SPKR) The counters in Timer 2

support fail-safe timeout functions and the CPU speed control

Integrated Support Logic

To minimize the chip count for board designs the ESC incorporates a number of extended features The ESC

provides support for ALTA20 (Fast A20GATE) and ALTRST with IO Port 92h The ESC generates the control

signals for SA address buffers and X-Bus buffer The ESC also provides chip selects for BIOS the keyboard

controller the floppy disk controller and three general purpose devices Support for generating chip selects

with an external decoder is provided for IDE a parallel port and a serial port The ESC provides support for a

PCAT compatible coprocessor interface and IRQ13 generation

Power Management (82374SB)

Extensive power management capability permits a system to operate in a low power state without being

powered down Once in the low power state (called ‘‘Fast Off’’ state) the computer appears to be off For

example the SMM code could turn off the CRT line printer hard disk drive’s spindle motor and fans In

addition the CPU’s clock can be governed To the user the machine appears to be in the off state However

the system is actually in an extremely low power state that still permits the CPU to function and maintain

communication connections normally associated with today’s desktops (eg LAN Modem or FAX) Program-

mable options provide power management flexibility For example various system events can be programmed

to place the system in the low power state or break events can be programmed to wake the system up

20 SIGNAL DESCRIPTION

This section provides a detailed description of each signal The signals are arranged in a functional group

according to their associated interface

The ‘‘ ’’ symbol at the end of a signal indicates that the active or asserted state occurs when the signal is at

a low voltage level When ‘‘ ’’ is not presented after the signal name the signal is asserted when at the high

voltage level

The terms assertion and negation are used extensively This is done to avoid confusion when working with a

mixture of ‘‘active-low’’ and ‘‘active-high’’ signals The term assert or assertion indicates that a signal is

active independent of whether that level is represented by a high or low voltage The term negate or

negation

indicates that a signal is inactive

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