82374EB datasheet(14/208 Pages) INTEL

14 / 208 page

82374EB82374SB

Integrated Bus Central Control Functions

The PCI-EISA Bridge chip set integrates central bus functions on both the PCI and EISA Buses For the PCI

Bus the functions include PCI bus arbitration and default bus driver For the EISA Bus central functions

include the EISA Bus controller and EISA arbiter are integrated in the ESC component and EISA Data Swap

Logic is integrated in the PCEB

Integrated System Functions

The PCI-EISA Bridge chip set integrates system functions including PCI parity and system errors reporting

buffer coherency management protocol PCI and EISA memory and IO address space mapping and decod-

ing For maximum flexibility all of these functions are programmable allowing for variety of optional features

11 PCEB Overview

The PCEB provides the interface (bridge) between PCI and EISA buses by translating bus protocols in both

directions It uses extensive buffering on both the PCI and EISA interfaces to allow concurrent bus operations

The PCEB also implements the PCI central support functions (eg PCI arbitration error signal support and

subtractive decoding) The major functions provided by the PCEB are described in this section

PCI Bus Interface

The PCEB can be either a master or slave on the PCI Bus and supports bus frequencies from 25 MHz to

33 MHz For PCI-initiated transfers the PCEB can only be a slave The PCEB becomes a slave when it

positively decodes the cycle The PCEB also becomes a slave for unclaimed cycles on the PCI Bus These

unclaimed cycles are either negatively or subtractively decoded by the PCEB and forwarded to the EISA Bus

As a slave the PCEB supports single cycle transfers for memory IO and configuration operations and burst

cycles for memory operations Note that burst transfers cannot be performed to the PCEB’s internal registers

Burst memory write cycles to the EISA Bus can transfer up to four Dwords depending on available space in

the PCEB’s Posted Write Buffers When space is no longer available in the buffers the PCEB terminates the

transaction This supports the Incremental Latency Mechanism as defined in the Peripheral Component Inter-

connect (PCI) Specification Note that if the Posted Write Buffers are disabled PCI burst operations are not

performed and all transfers are single cycle

For EISA-initiated transfers to the PCI Bus the PCEB is a PCI master The PCEB permits EISA devices to

access either PCI memory or IO While all PCI IO transfers are single cycle PCI memory cycles can be

either single cycle or burst depending on the status of the PCEB’s Line Buffers During EISA reads of PCI

memory The PCEB uses a burst read cycle of four Dwords to prefetch data into a Line Buffer During EISA-to-

PCI memory writes the PCEB uses PCI burst cycles to flush the Line Buffers The PCEB contains a program-

mable Master Latency Timer that provides the PCEB with a guaranteed time slice on the PCI Bus after which it

surrenders the bus

As a master on the PCI Bus the PCEB generates address and command signal (CBE ) parity for read and

write cycles and data parity for write cycles As a slave the PCEB generates data parity for read cycles Parity

checking is not supported

The PCEB as a resource can be locked by any PCI master In the context of locked cycles the entire PCEB

subsystem (including the EISA Bus) is considered a single resource

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