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82374EB Folha de dados(PDF) 53 Page - Intel Corporation

Nome de Peças 82374EB
Descrição Electrónicos  SYSTEM COMPONENT (ESC)
PDF  208 Pages
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Fabricante Electrônico  INTEL [Intel Corporation]
Página de início  http://www.intel.com
Logo INTEL - Intel Corporation

82374EB Folha de dados(HTML) 53 Page - Intel Corporation

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consists of two logical channel groups – Channels 0-3 (Controller 1-DMA1) and Channels 4-7 (Controller 2-
DMA2) Both groups may be assigned fixed priority one group can be assigned fixed priority and the second
rotating priority or both groups may be assigned rotating priority A detailed description of the channel priority
scheme is found in the DMA functional description Section 65 Following a reset or DMA Master Clear both
DMA-1 and DMA-2 are enabled in fixed priority the DREQ sense level is active high and the DACK
assertion level is active low
Bit
Description
7
DACK
Assert Level
Bit 7 controls the DMA channel request acknowledge (DACK ) assertion
level Following reset the DACK
assertion level is active low The low level indicates recognition and
acknowledgment of the DMA request to the DMA slave requesting service Writinga0tobit7 assigns
active low as the assertion level Whena1is written to this bit a high level on the DACK
line
indicates acknowledgment of the request for DMA service to the DMA slave
6
DREQ Sense Assert Level
Bit 6 controls the DMA channel request (DREQ) assertion detect level
Following reset the DREQ sense assert level is active high In this condition an active high level
sampled on DREQ is decoded as an active DMA channel request Writinga0tobit6 assigns active
high as the sense assert level Whena1is written to this bit a low level on the DREQ line is decoded
as an active DMA channel request
5
Reserved
Must be 0
4
DMA Group Arbitration
Each channel group is individually assigned either fixed or rotating arbitration
priority At reset each group is initialized in fixed priority Writinga0tobit4 assigns fixed priority to the
channel group while writing a 1 assigns rotating priority to the group
3
Reserved
Must be 0
2
DMA Group Enable
Writinga1to this bit disables the DMA channel group while writinga0to this bit
enables the DMA channel group Both channel groups are enabled following reset Disabling Channel
group 4-7 also disables Channel group 0-3 which is cascaded through Channel 4
10
Reserved
Must be 0
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