AD9775 datasheet(30/56 Pages) AD

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AD9775

Rev. E | Page 30 of 56

ONEPORTCLK DRIVER STRENGTH

The drive capability of ONEPORTCLK is identical to that of

DATACLK in the two-port mode. Refer to Figure 53 for

performance under load conditions.

IQ PAIRING

(Control Register 0x02, Bit 0)

In one-port mode, the interleaved data is latched into the

AD9775 internal I and Q channels in pairs. The order of how

the pairs are latched internally is defined by this control register.

The following is an example of the effect that this has on

incoming interleaved data.

Given the following interleaved data stream, where the data

indicates the value with respect to full scale:

Table 20.

0.5

With the control register set to 0 (I first), the data appears at the

internal channel inputs in the following order in time:

Table 21.

I Channel

0.5

Q Channel

0.5

With the control register set to 1 (Q first), the data appears at

the internal channel inputs in the following order in time:

Table 22.

I Channel

0.5

Q Channel

0.5

The values x and y represent the next I value and the previous

Q value in the series.

PLL DISABLED, TWO-PORT MODE

With the PLL disabled, a clock at the DAC output rate must be

applied to CLKIN. Internal clock dividers in the AD9775

synthesize the DATACLK signal at Pin 8, which runs at the

input data rate and can be used to synchronize the input data.

Data is latched into input Port 1 and Port 2 of the AD9775 on

the rising edge of DATACLK. DATACLK speed is defined as the

speed of CLKIN divided by the interpolation rate. With zero

stuffing enabled, this division increases by a factor of 2. Figure 55

illustrates the delay between the rising edge of CLKIN and the

rising edge of DATACLK, as well as tS and tH in this mode.

The programmable modes DATACLK inversion and DATACLK

driver strength described in the previous section (PLL Enabled,

Two-Port Mode) have identical functionality with the PLL

disabled.

The data rate clock created by dividing down the DAC clock in

this mode can be programmed (via Register 0x03, Bit 7) to be

output from the SPI_SDO pin rather than the DATACLK/

PLL_LOCK pin. In some applications, this may improve

complex image rejection. When SPI_SDO is used as data rate

clock out, tOD increases by 1.6 ns.

tOD

tOD = 6.5ns (MIN) TO 8.0ns (MAX)

tS = 5.0ns (MIN)

tH = –3.2ns (MIN)

CLKIN

DATACLK

DATA AT PORTS

1 AND 2

Figure 55. Timing Requirements in Two-Port Input Mode with PLL Disabled

tOD

tIQS

tIQH

tOD = 4.0ns (MIN)

TO 5.5ns (MAX)

tS = 3.0ns (MIN)

tH = –1.0ns (MIN)

tIQS = 3.5ns (MIN)

tIQH = –1.5ns (MIN)

CLKIN

IQSEL

ONEPORTCLK

I AND Q INTERLEAVED

INPUT DATA AT PORT 1

Figure 56. Timing Requirements in One-Port Input Mode with PLL Disabled

PLL DISABLED, ONE-PORT MODE

In one-port mode, data is received into the AD9775 as an

interleaved stream on Port 1. A clock signal (ONEPORTCLK)

running at the interleaved data rate, which is 2× the input data

rate of the internal I and Q channels, is available for data

synchronization at Pin 32.

With PLL disabled, a clock at the DAC output rate must be

applied to CLKIN. Internal dividers synthesize the

ONEPORTCLK signal at Pin 32. The selection of the data for

the I or Q channel is determined by the state of the logic level

applied to Pin 31 (IQSEL when the AD9775 is in one-port

mode) on the rising edge of ONEPORTCLK. Under these

conditions, IQSEL = 0 latches the data into the I channel on the

clock rising edge, while IQSEL = 1 latches the data into the Q

channel.

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