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AD9775

Rev. E | Page 27 of 56

In addition, if the zero-stuffing option is enabled, the VCO

doubles its speed again. Phase noise may be slightly higher with

the PLL enabled. Figure 47 illustrates typical phase noise perform-

ance of the AD9775 with 2× interpolation and various input

data rates. The signal synthesized for the phase noise measurement

was a single carrier at a frequency of fDATA/4. The repetitive

nature of this signal eliminates quantization noise and distortion

spurs as a factor in the measurement. Although the curves blend

together in Figure 47, the different conditions are given for clarity

in Table 19. Figure 47 also contains a table detailing the maximum

and minimum fDATA rates for each combination of interpolation

rate and PLL divider setting. These rates are guaranteed over

the entire supply and operating temperature range. Figure 48

shows typical performance of the PLL lock signal (Pin 8 or

Pin 53) when the PLL is in the process of locking.

Table 19. Required PLL Prescaler Ratio vs. fDATA

fDATA

PLL

Prescaler Ratio

125 MSPS

Disabled

125 MSPS

Enabled

Div 1

100 MSPS

Enabled

Div 2

75 MSPS

Enabled

Div 2

50 MSPS

Enabled

Div 4

–110

–100

–80

–40

–20

–60

–90

–50

–30

–10

–70

012

FREQUENCY OFFSET (MHz)

Figure 47. Phase Noise Performance

Figure 48. PLL_LOCK Output Signal (Pin 8) in the Process of Locking

(Typical Lock Time)

It is important to note that the resistor/capacitor needed for the

PLL loop filter is internal on the AD9775. This suffices unless the

input data rate is below 10 MHz, in which case an external series

RC is required between the LPF pin and CLKVDD pins.

POWER DISSIPATION

The AD9775 has three voltage supplies: DVDD, AVDD, and

CLKVDD. Figure 49 through Figure 51 show the current

required from each of these supplies when each is set to the 3.3 V

nominal specified for the AD9775. Power dissipation (PD) can

easily be extracted by multiplying the given curves by 3.3. As

Figure 49 shows, IDVDD is very dependent on the input data rate,

the interpolation rate, and the activation of the internal digital

modulator. IDVDD, however, is relatively insensitive to the

modulation rate by itself. In Figure 50, IAVDD shows the same type

of sensitivity to the data, the interpolation rate, and the modu-

lator function but to a much lesser degree (<10%). In Figure 51,

ICLKVDD varies over a wide range yet is responsible for only a small

percentage of the overall AD9775 supply current requirements.

100

150

200

250

300

350

400

fDATA (MHz)

100

150

200

×, (MOD. ON)

Figure 49. IDVDD vs. fDATA vs. Interpolation Rate, PLL Disabled

×, (MOD. ON)

72.0

72.5

73.0

73.5

74.0

74.5

75.0

75.5

76.0

fDATA (MHz)

100

150

200

×, (MOD. ON)

Figure 50. IAVDD vs. fDATA vs. Interpolation Rate, PLL Disabled

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