HD6433636SW datasheet(280/418 Pages) RENESAS

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Receiving Multiprocessor Ddata: Figure 10.22 shows a typical flow chart for receiving data

using a multiprocessor format. After SCI3 initialization, follow the procedure below.

Start

Set bit MPIE in SCR3 to 1

Read bits OER and FER in SSR

Read bit RDRF in SSR

RDRF = 1?

Read received data in RDR

OER + FER = 1?

Read bits OER and FER in SSR

Continue receiving?

End

Clear bit RE in SCR3 to 0

Start receive error processing

OER = 1?

FER = 1?

Clear bits OER and

FER in SSR to 0.

Overrun error

processing

Break?

Framing error

processing

Set bit MPIE in serial control register 3 (SCR3) to 1.

Read bits OER and FER in the serial status register (SSR)

to determine if an error has occurred. If a receive error has

occurred, receive error processing is executed.

Read SSR, check that bit RDRF = 1, then read received

data from the receive data register (RDR).

If a receive error occurs, read bits OER and FER in SSR

to determine which error occurred. After the necessary

error processing, be sure to clear the error flags to 0.

Data reception cannot resume while bit OER or FER is

set to 1.

When a framing error occurs, a break can be detected by

reading the RXD pin value.

Yes

Error processing

Read received data in RDR

End receive error processing

Own ID?

Read bit RDRF in SSR

OER + FER = 1?

Yes

RDRF = 1?

Yes

If the received data does not match the ID, set bit MPIE to

1 again. Bit RDRF is automatically cleared to 0 when data

in the received data register (RDR) is read.

Read the serial status register (SSR) and confirm that

RDRF = 1. If RDRF = 1, read the data in the received data

Figure 10.22 Typical Flow Chart for Receiving Serial Data Using Multiprocessor Format

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