HD6433636SW datasheet(282/418 Pages) RENESAS

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10.3.7

Interrupts

SCI3 has six interrupt sources: transmit end, transmit data empty, receive data full, and the three

receive error interrupts (overrun error, framing error, and parity error). All share a common

interrupt vector. Table 10.16 describes each interrupt.

Table 10.16 SCI3 Interrupts

Interrupt

Interrupt Request

Vector Address

RXI

Interrupt request due to receive data register full (RDRF)

H'0024

TXI

Interrupt request due to transmit data register empty (TDRE)

TEI

Interrupt request due to transmit end (TEND)

ERI

Interrupt request due to receive error (OER, FER, or PER)

The interrupt requests are enabled and disabled by bits TIE and RIE of SCR3.

When bit TDRE in SSR is set to 1, TXI is requested. When bit TEND in SSR is set to 1, TEI is

requested. These two interrupt requests occur during data transmission.

The initial value of bit TDRE is 1. Accordingly, if the transmit data empty interrupt request (TXI)

is enabled by setting bit TIE to 1 in SCR3 before placing transmit data in TDR, TXI will be

requested even though no transmit data has been readied.

Likewise, the initial value of bit TEND is 1. Accordingly, if the transmit end interrupt request

(TEI) is enabled by setting bit TEIE to 1 in SCR3 before placing transmit data in TDR, TEI will be

requested even though no data has been transmitted.

These interrupt features can be used to advantage by programming the interrupt handler to move

the transmit data into TDR. When this technique is not used, the interrupt enable bits (TIE and

TEIE) should not be set to 1 until after TDR has been loaded with transmit data, to avoid

unwanted TXI and TEI interrupts.

When bit RDRF in SSR is set to 1, RXI is requested. When any of SSR bits OER, FER, or PER is

set to 1, ERI is requested. These two interrupt requests occur during the receiving of data.

Details on interrupts are given in 3.3, Interrupts.

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