HD6433636SW datasheet(279/418 Pages) RENESAS

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SCI3 operates as follows during data transmission using a multiprocessor format.

SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data

written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR).

Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is

requested.

Serial data is transmitted from pin TXD using the communication format outlined in

table 10.14.

Next, TDRE is checked as the stop bit is being transmitted. If TDRE is 0, data is transferred from

TDR to TSR, and after the stop bit is sent, transmission of the next frame starts. If TDRE is 1, the

TEND bit in SSR is set to 1, and after the stop bit is sent the output remains at 1 (mark state). A

TEI interrupt is requested in this state if bit TEIE (transmit end interrupt enable) in SCR3 is set

to 1.

Figure 10.21 shows a typical SCI3 operation in multiprocessor communication mode.

0D0

0/1

Start

bit

Start

bit

Stop

bit

Stop

bit

MPB

TDRE

TEND

TDRE cleared

to 0

TXI

request

TEI

request

1 frame

TXI request

Serial

data

Transmit

data

Transmit

data

Mark

state

1 frame

SCI3

operation

User

processing

Write data in

TDR

Figure 10.21 Typical Multiprocessor Format Transmit Operation

(8-Bit Data, Multiprocessor Bit Added, and 1 Stop Bit)

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