HD6433636SW datasheet(235/418 Pages) RENESAS

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6. Read the received data from SDRL and SDRU, as follows.

8-bit transfer mode:

SDRL

16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL

When an internal clock is used, a serial clock is output from pin SCK

1 in synchronization with the

transmit data. After data transmission is complete, the serial clock is not output until the next time

the start flag is set to 1. During this time, pin SO

1 continues to output the value of the last bit

transmitted.

When an external clock is used, data is transmitted and received in synchronization with the serial

clock input at pin SCK

1. After data transmission and reception are complete, an overrun occurs if

the serial clock continues to be input; no data is transmitted or received and the SCSR1 overrun

error flag (bit ORER) is set to 1.

While transmission is stopped, the output value of pin SO

1 can be changed by rewriting bit SOL in

SCSR1.

10.2.4

Interrupt Sources

SCI1 can generate an interrupt at the end of a data transfer.

When an SCI1 transfer is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1.

SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 1

(IENR1).

For further details, see 3.3, Interrupts.

10.2.5

Usage Notes

Note the following points when using SCI1.

1. When an external clock is input to the SCK1 pin

When SCK1 is designated as an input pin and an external clock is selected as the clock source,

do not input the external clock before writing 1 to the STF bit in SCSR1 to start the transfer

operation.

2. Confirming the end of serial transfer

Do not read or write to SCSR1 during serial transfer. The following two methods can be used

to confirm the end of serial transfer:

a. Using SCI1 interrupt exception handling

Set the IENS1 bit to 1 in IENR1 and execute interrupt exception handling.

b. Using IRR1 polling

With SCI1 interrupts disabled (IENS1 = 0 in IENR1), confirm that the IRRS1 bit in IRR1

has been set to 1.

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