HD6433636SW datasheet(231/418 Pages) RENESAS

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Bit 6—Extended Data Bit (SOL): Bit 6 sets the SO

1 output level. When read, SOL returns the

output level at the SO

1 pin. After completion of a transmission, SO1 continues to output the value

of the last bit of transmitted data. The SO

1 output can be changed by writing to SOL before or

after a transmission. The SOL bit setting remains valid only until the start of the next transmission.

To control the level of the SO

1 pin after transmission ends, it is necessary to write to the SOL bit at

the end of each transmission. Do not write to this register while transmission is in progress,

because that may cause a malfunction.

Bit 6: SOL

Description

Read

1 pin output level is low

(initial value)

Write

1 pin output level changes to low

Read

1 pin output level is high

Write

1 pin output level changes to high

Bit 5—Overrun Error Flag (ORER): When an external clock is used, bit 5 indicates the

occurrence of an overrun error. If a clock pulse is input after transfer completion, this bit is set to 1

indicating an overrun. If noise occurs during a transfer, causing an extraneous pulse to be

superimposed on the normal serial clock, incorrect data may be transferred.

Bit 5: ORER

Description

[Clearing conditions]

(initial value)

After reading ORER = 1, cleared by writing 0 to ORER

[Setting conditions]

Set if a clock pulse is input after transfer is complete, when an external clock

is used

Bits 4 to 2—Reserved Bits: Bits 4 to 2 are reserved; they are always read as 1, and cannot be

modified.

Bit 1—Reserved Bit: Bit 1 is reserved; and cannot be modified. This bit will be read as 0 after a

reset, but its value is undefined at other times.

Bit 0—Start Flag (STF): Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to

start transferring data.

During the transfer or while waiting for start bit, this bit remains set to 1. It is cleared to 0 upon

completion of the transfer.

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