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HD6433636SW Folha de dados(PDF) 238 Page - Renesas Technology Corp |
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HD6433636SW Folha de dados(HTML) 238 Page - Renesas Technology Corp |
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238 / 418 page ![]() 224 Pin Configuration: Table 10.4 shows the SCI3 pin configuration. Table 10.4 Pin Configuration Name Abbrev. I/O Function SCI3 clock SCK 3 I/O SCI3 clock input/output SCI3 receive data input RXD Input SCI3 receive data input SCI3 transmit data output TXD Output SCI3 transmit data output Register Configuration: Table 10.5 shows the SCI3 internal register configuration. Table 10.5 SCI3 Registers Name Abbrev. R/W Initial Value Address Serial mode register SMR R/W H'00 H'FFA8 Bit rate register BRR R/W H'FF H'FFA9 Serial control register 3 SCR3 R/W H'00 H'FFAA Transmit data register TDR R/W H'FF H'FFAB Serial status register SSR R/W H'84 H'FFAC Receive data register RDR R H'00 H'FFAD Transmit shift register TSR Not possible — — Receive shift register RSR Not possible — — Bit rate counter BRC Not possible — — 10.3.2 Register Descriptions Receive Shift Register (RSR) 7 — 6 — 5 — 4 — 3 — 0 — 2 — 1 — Bit Read/Write The receive shift register (RSR) is for receiving serial data. Serial data is input in LSB-first order into RSR from pin RXD, converting it to parallel data. After each byte of data has been received, the byte is automatically transferred to the receive data register (RDR). RSR cannot be read or written directly by the CPU. |
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