HD6433636SW datasheet(195/418 Pages) RENESAS

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Compare Match Flag Set Timing: The compare match flags (CMFH or CMFL) are set to 1

when a compare match occurs between TCF and OCRF. A compare match signal is generated in

the final state in which the values match (when TCF changes from the matching count value to the

next value). When TCF and OCRF match, a compare match signal is not generated until the next

counter clock pulse.

Timer F Operation States: Table 9.7 summarizes the timer F operation states.

Table 9.7

Timer F Operation States

Operation Mode

Reset

Active

Sleep

Watch

Sub-

active

Sub-

sleep

Standby

TCF

Reset

Functions

Halted

OCRF

Reset

Functions

Retained

TCRF

Reset

Functions

Retained

TCSRF

Reset

Functions

Retained

9.3.5

Application Notes

The following conflicts can arise in timer F operation.

16-Bit Timer Mode: The output at pin TMOFH toggles when all 16 bits match and a compare

match signal is generated. If the compare match signal occurs at the same time as new data is

written in TCRF by a MOV instruction, however, the new value written in bit TOLH will be

output at pin TMOFH. The TMOFL output in 16-bit mode is indeterminate, so this output should

not be used. Use the pin as a general input or output port.

If an OCRFL write occurs at the same time as a compare match signal, the compare match signal

is inhibited. If a compare match occurs between the written data and the counter value, however, a

compare match signal will be generated at that point. The compare match signal is output in

synchronization with the TCFL clock, so if this clock is stopped no compare match signal will be

generated, even if a compare match occurs.

Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated;

bit CMFL is set when the setting conditions are met for the lower 8 bits.

The overflow flag (OVFH) is set when TCF overflows; bit OVFL is set if the setting conditions

are met when the lower 8 bits overflow. If a write to TCFL occurs at the same time as an overflow

signal, the overflow signal is not output.

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