HD6433636SW datasheet(193/418 Pages) RENESAS

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9.3.4

Timer Operation

Timer F is a 16-bit timer/counter that increments with each input clock. When the value set in

output compare register F matches the count in timer F, the timer can be cleared, an interrupt can

be requested, and the port output can be toggled. Timer F can also be used as two independent

8-bit timers.

Timer F Operation: Timer F can operate in either 16-bit timer mode or 8-bit timer mode. These

modes are described below.

• 16-bit timer mode

Timer F operates in 16-bit timer mode when the CKSH2 bit in timer control register F (TCRF)

is cleared to 0.

A reset initializes timer counter F (TCF) to H'0000, output compare register F (OCRF) to

H'FFFF, and timer control register F (TCRF) and timer control status register F (TCSRF) to

H'00. Timer F begins counting external event input signals (TMIF). The edge of the external

event signal is selected by the IEG3 bit in the IRQ edge select register (IEGR).

The operational clock of timer F can be selected by setting bits CSKL2 through CKSL0 in

TCRF, from four internal clocks output from prescaler S as well as from an external clock.

TCF is continuously compared with the contents of OCRF. When these two values match, the

CMFH bit in TCSRF is set to 1. At this time if IENTFH of IENR2 is 1, a CPU interrupt is

requested and the output at pin TMOFH is toggled. If the CCLRH bit in TCSRF is 1, TCF is

cleared. The output at pin TMOFH can also be set by the TOLH bit in TCRF.

If timer F overflows (from H'FFFF to H'0000), the OVFH bit in TCSRF is set to 1. At this

time, if the OVIEH bit in TCSRF and the IENTFH bit in IENR2 are both 1, CPU interrupt is

requested.

• 8-bit timer mode

When the CKSH2 bit in TCRF is set to 1, timer F operates as two independent 8-bit timers,

TCFH and TCFL. The input clock of TCFH/TCFL is selected by bits CKSH2 to

CKSH0/CKSL2 to CKSL0 in TCRF.

When TCFH/TCFL and the contents of OCRFH/OCRFL match, the CMFH/CMFL bit in

TCSRF is set to 1. If the IENTFH/IENTFL bit in IENR2 is 1, a CPU interrupt is requested and

the output at pin TMOFH/TMOFL is toggled. If the CCLRH/CCLRL bit in TCRF is 1,

TCFH/TCFL is cleared. The output at pin TMOFH/TMOFL can also be set by the

TOLH/TOLL bit in TCRF.

When TCFH/TCFL overflows from H'FF to H'00, the OVFH/OVFL bit in TCSRF is set to 1.

At this time, if the OVIEH/OVIEL bit in TCSRF and the IENTFH/IENTFL bit in IENR2 are

both 1, a CPU interrupt is requested.

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