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5.8

Direct Transfer

5.8.1

Overview

The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed)

mode, and subactive mode. A direct transfer is a transition among these three modes without the

stopping of program execution. A direct transfer can be made by executing a SLEEP instruction

while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt

exception handling starts.

If the direct transfer interrupt is disabled in interrupt enable register 2 (IENR2), a transition is

made instead to sleep mode or watch mode. Note that if a direct transition is attempted while the I

bit in CCR is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear

the resulting mode by means of an interrupt.

Direct Transfer from Active (High-Speed) Mode to Active (Medium-Speed) Mode: When a

SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in

SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is

set to 1, a transition is made to active (medium-speed) mode via sleep mode.

Direct Transfer from Active (High-Speed) Mode to Active (High-Speed) Mode: When a

SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in

SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in

SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode.

Direct Transfer from Active (High-Speed) Mode to Subactive Mode: When a SLEEP

instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1

are set to 1, the DTON bit in SYSCR2 is set to 1, and bit TMA3 in TMA is set to 1, a transition is

made to subactive mode via watch mode.

Direct Transfer from Subactive Mode to Active (High-Speed) Mode: When a SLEEP

instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit

in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is

set to 1, and bit TMA3 in TMA is set to 1, a transition is made directly to active (high-speed)

mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed.

Direct Transfer from Active (Medium-Speed) Mode to Subactive Mode: When a SLEEP

instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in

SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and bit TMA3 in TMA is set to 1, a

transition is made to subactive mode via watch mode.

Direct Transfer from Subactive Mode to Active (Medium-Speed) Mode: When a SLEEP

instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit

in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in SYSCR2 is set

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