HD6433636SW datasheet(116/418 Pages) RENESAS

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5.7

Active (medium-speed) Mode

5.7.1

Transition to Active (medium-speed) Mode

If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition

to active (medium-speed) mode results from IRQ

0, IRQ1, or WKP0 to WKP7 interrupts in standby

mode, timer A, IRQ

0, or WKP0 to WKP7 interrupts in watch mode, or any interrupt in sleep mode.

A transition to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or

the particular interrupt is disabled in the interrupt enable register.

5.7.2

Clearing Active (medium-speed) Mode

Active (medium-speed) mode is cleared by a SLEEP instruction or by a low input at the reset.

Clearing by SLEEP Instruction: A transition to standby mode takes place if a SLEEP

instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is

cleared to 0, and bit TMA3 in TMA is cleared to 0. The system goes to watch mode if the SSBY

bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1 when a SLEEP instruction is executed.

Sleep mode is entered if both SSBY and LSON are cleared to 0 when a SLEEP instruction is

executed. Direct transfer to active (high-speed) mode or to subactive mode is also possible. See

5.8, Direct Transfer, below for details.

Clearing by Reset: When the

RES pin goes low, or when a watchdog timer reset is effected, the

CPU goes into the reset state and active (medium-speed) mode is cleared.

5.7.3

Operating Frequency in Active (medium-speed) Mode

In active (medium-speed) mode, the CPU is clocked at 1/8 the frequency in active (high-speed)

mode. The DTMF generator, however, continues to operate on the OSC clock (ø

OSC).

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