AD6677 datasheet(30/48 Pages) AD

30 / 48 page

AD6677

Data Sheet

Rev. C | Page 30 of 48

–0.5

0.5

ULS

PERIOD1: HISTOGRAM

6000

7000

–10

TIME (ps)

5000

4000

1000

2000

3000

1–16

1–14

1–12

1–10

1–8

1–6

1–4

1–2

–

–100

–200

100

200

TIME (ps)

400

300

200

100

–100

–300

–400

–200

HEIGHT1: EYE DIAGRAM

–

TJ AT BER1: BATHTUB

EYE: ALL BITS OFFSET: 0

ULS: 7000; 993329 TOTAL: 7000; 993329

Figure 56. AD6677 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations at 5 Gbps

ADC OVERRANGE AND GAIN CONTROL

In receiver applications, it is desirable to have a mechanism to

reliably determine when the converter is about to be clipped.

The standard overflow indicator provides delayed information on

the state of the analog input that is of limited value in preventing

clipping. Therefore, it is helpful to have a programmable threshold

below full scale that allows time to reduce the gain before the

clip occurs. In addition, because input signals can have significant

slew rates, latency of this function is of concern.

Using the SPI port, the user can provide a threshold above which

the FD output is active. Bit 0 of Address 0x45 enables the fast

detect feature. Address 0x47 to Address 0x4A allow the user to

set the threshold levels. As long as the signal is below the selected

threshold, the FD output remains low. In this mode, the magnitude

of the data is considered in the calculation of the condition, but

the sign of the data is not considered. The threshold detection

responds identically to positive and negative signals outside the

desired range (magnitude).

ADC Overrange (OR)

The ADC overrange indicator is asserted when an overrange is

detected on the input of the ADC. The overrange condition is

determined at the output of the ADC pipeline and, therefore, is

subject to a latency of 36 ADC clock cycles. An overrange at the

input is indicated by this bit 36 clock cycles after it occurs.

Gain Switching

The AD6677 includes circuitry that is useful in applications

either where large dynamic ranges exist, or where gain ranging

amplifiers are employed. This circuitry allows digital thresholds

to be set such that an upper threshold and a lower threshold can

be programmed.

One such use is to detect when an ADC is about to reach full

scale with a particular input condition. The result is to provide

an indicator that can be used to quickly insert an attenuator that

prevents ADC overdrive.

Fast Threshold Detection (FD)

The FD indicator is asserted if the input magnitude exceeds the

value programmed in the fast detect upper threshold registers,

located in Address 0x47 and Address 0x48. The selected threshold

the ADC. The fast upper threshold detection has a latency of

four clock cycles. The approximate upper threshold magnitude

is defined by

Upper Threshold Magnitude (dBFS) = 20 log (Threshold

Magnitude/213)

The FD indicators are not cleared until the signal drops below

the lower threshold for the programmed dwell time. The lower

threshold is programmed in the fast detect lower threshold

registers, located at Address 0x49 and Address 0x4A. The fast

detect lower threshold register is a 16-bit register that is compared

with the signal magnitude at the output of the ADC. This

comparison is subject to the ADC pipeline latency but is

accurate in terms of converter resolution. The lower threshold

magnitude is defined by

Lower Threshold Magnitude (dBFS) = 20 log (Threshold

Magnitude/213)

For example, to set an upper threshold of −6 dBFS, write

0x0FFF to those registers, and to set a lower threshold of

−10 dBFS, write 0x0A1D to those registers.

The dwell time can be programmed from 1 to 65,535 sample

clock cycles by placing the desired value in the fast detect dwell

time registers, located in Address 0x4B and Address 0x4C.

The operation of the upper threshold and lower threshold registers,

along with the dwell time registers, is shown in Figure 57.

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