AD6677

Data Sheet

Rev. C | Page 4 of 48

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range,

duty cycle stabilizer enabled, default SPI, unless otherwise noted.

Table 1.

Parameter

Temperature

Min

Typ

Max

Unit

RESOLUTION

Full

11

Bits

ACCURACY

No Missing Codes

Full

Guaranteed

Offset Error

Full

±9.0

mV

Gain Error

Full

−5.3

+1.2

%FSR

Differential Nonlinearity (DNL)

Full

±0.6

LSB

25°C

±0.25

LSB

Full

±0.7

LSB

25°C

±0.3

LSB

TEMPERATURE DRIFT

Offset Error

Full

±7

ppm/°C

Gain Error

Full

±39

ppm/°C

INPUT REFERRED NOISE

VREF = 1.75 V

25°C

0.46

LSB rms

ANALOG INPUT

Input Span

Full

1.75

V p-p

Full

2.5

pF

Full

20

kΩ

Input Common-Mode Voltage

Full

0.9

V

POWER SUPPLIES

Supply Voltage

AVDD

Full

1.7

1.8

1.9

V

DRVDD

Full

1.7

1.8

1.9

V

DVDD

Full

1.7

1.8

1.9

V

Supply Current

Full

149

163

mA

Full

mA

NSR Disabled

Full

93

mA

NSR Enabled, 22% Mode

Full

120

128

mA

NSR Enabled, 33% Mode

Full

129

mA

POWER CONSUMPTION

Sine Wave Input

Full

NSR Disabled

Full

435

mW

NSR Enabled, 22% Mode

Full

484

mW

NSR Enabled, 33% Mode

Full

500

mW

Full

266

mW

Full

9

mW

1

Measured with a low input frequency, full-scale sine wave.

2

Input capacitance refers to the effective capacitance between one differential input pin and the complement.

3

Input resistance refers to the effective resistance between one differential input pin and the complement.

4

Standby power is measured with a low input frequency, full-scale sine wave and the CLK± pins active. Address 0x08 is set to 0x20, and the PDWN pin is asserted.

5

Power-down power is measured with a low input frequency, full-scale sine wave, RFCLK pulled high, and the CLK± pins active. Address 0x08 is set to 0x00 and the

PDWN pin is asserted.