AD6677 datasheet(22/48 Pages) AD

22 / 48 page

AD6677

Data Sheet

Rev. C | Page 22 of 48

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 44, the power dissipated by the AD6677 is

proportional to the sample rate. The data in Figure 44 was taken

using the same operating conditions as those used for the Typical

Performance Characteristics section. IDVDD in Figure 44 is a

summation of IDVDD and IDRVDD.

0.05

0.10

0.15

0.20

0.25

0.1

0.2

0.3

0.4

0.5

40 55 70 85 100 115 130 145 160 175 190 205 220 235 250

ENCODE FREQUENCY (MSPS)

IAVDD

TOTAL POWER

IDVDD

Figure 44. Power vs. Encode Rate

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the AD6677 is placed in power-down mode.

In this state, the ADC typically dissipates about 9 mW. Asserting the

PDWN pin low returns the AD6677 to the normal operating mode.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering power-

down mode and then must be recharged when returning to normal

operation. As a result, wake-up time is related to the time spent

in power-down mode, and shorter power-down cycles result in

proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map Register

Descriptions section and theApplication Note AN-877, Interfacing

to High Speed ADCs via SPI, for additional details.

AD6677 Folha de dados(PDF) 22 Page - Analog Devices

AD6677 Folha de dados(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Folha de dados Download

Ligação URL